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mb9b120m series 32 - b it a rm ? cortex ? - m 3 fm 3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05655 rev. *d revised february 9 , 2018 the mb9b 120m series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with low - p ower consumption mode and competitive cost. th ese s eries are based on the a rm ? cortex ? - m3 processor with on - chip flash memory and sram, and ha ve peripheral functions such as various t imers, adcs , dacs and communication interfaces (uart, c sio, i 2 c, lin). the products which are described in this data sheet are placed into type 9 product categories in fm3 family p eripheral m anual . f eature s 32 - bit a rm ? cortex ? - m3 core ? processor version: r2p1 ? up to 72 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memory] ? dual operation flash memory ? dual operation flash memory has the upper bank and the lower bank. so, this series could implement erase, write and read operations for each bank simultaneously. ? main area: up to 256 kbytes (up to 240 kbytes upper bank + 16 kbytes lower bank) ? wo rk area: 32 kbytes (lower bank) ? read cycle: 0 wait - cycle ? security function for code protection [sram] this series on - chip sram is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 16 kbytes ? sram1: up to 16 kbytes multi - function serial interface ( max eight channels ) ? 4 channels with 16 stepsx9 - bit fifo (ch.0/1/3/4), 4 channels without fifo (ch.2/5/6/7) ? operation mode is selectable from the followi ngs for each channel. ? uart ? csio ? lin ? i 2 c [ uart ] ? full duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control: automatically control the transmis sion /reception by cts/rts (only ch.4) ? various error detection functions available (parity errors, framing errors, and overrun errors) [ csio ] ? full duplex double buffer ? built - in dedicated baud rate g enerator ? overrun error detection function available [ lin ] ? lin protocol rev.2.1 supported ? full duplex double buffer ? master /slave mode supported ? lin break field generation (can be changed to 13 to 16 - bit length) ? lin break delimiter generation (can be changed to 1 to 4 - bit length) ? various error detection functions a vailable (parity errors , framing errors , and overrun errors) [i 2 c] ? standard mode (max 100 kbps)/fast mode (max 400 kbps) supported
document number: 002 - 05655 rev. *d page 2 of 101 mb9b120m series dma controller ( eight channels) the dma c ontroller has an independent bus from the cpu, so the cpu and the dma c ontroller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 - bit (4 gbytes) ? transfer mode: block transfer/ burst transfer/demand transfer ? transfer data type: bytes/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 a/d converter ( max 2 6 channels) [ 12 - bit a/d converter ] ? successive approximation type ? built - in 2 units ? conversion time: 0.8 v# 5 v ? priority conversion available (priority at 2 levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for p riority conversion: 4 steps) d / a converter (max two channels) ? r - 2r type ? 10 - bit resolution base timer (max eight channels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer general - purpose i/o port this series can use its pins as general - purpose i/o ports when they are not used for peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated to . ? capable of pull - up control per pin ? capable of reading pin level directly ? buil t - in port relocate function ? up to 65 high - speed general - purpose i/o ports @ 80 pin p ackage ? some ports are 5v tolerant. see " list of pin functions " and " i / o circuit type " to confirm the corresponding pins. dual timer (32 - /16 - bit down counter) the d ual t imer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each channel. ? free - running ? periodic (=reload) ? one - shot quadrature position/revolution counter (qprc) (max two c hannels) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use as the up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16 - b it position counter ? 16 - bit revolution counter ? two 16 - bit compare registers
document number: 002 - 05655 rev. *d page 3 of 101 mb9b120m series multi - f unction timer the m ulti - function timer is composed of the following blocks. ? 16 - bit free - run timer 3ch. /unit ? input capture 4ch. /unit ? output compare 6ch. /unit ? a/d activ ation compare 2 ch. /unit ? waveform generator 3ch. /unit ? 16 - bit ppg timer 3ch. /unit the following function s can be used to achieve motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convert e r activate function ? dtif ( m otor emergency stop) interrupt function real - t ime c lock (rtc) the r eal - time clock can count year/month/day/hour/minute/second/a day of the week from 0 0 to 99. ? the i nterrupt function with specifying date and time (year/month/day/hour/minute) is available. this function is also available by specifying only year, month, day, hour or minute. ? timer interrupt function after set time or each set time. ? capable of rewriting the time with continuing the time count. ? leap yea r automatic count is available. watch counter the w atch counter is used for wake up from the sleep and timer mode. interval timer: up to 64 s (max) @ sub clock: 32.768 khz external interrupt controller unit ? up to 23 e xte rnal interrupt input pin s @ 80 pin package ? include one non - maskable interrupt (nmi) input pin watchdog timer ( two c hannels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a 3+ ardwar e watchdog and a 36 oftware watchdog. the 3+ ardware watchdog timer is clocked by the built - in low - speed cr oscillator. therefore, the 3+ ardware watchdog is active in any low - power consumption mode s except rtc , stop, deep standby rtc, deep standby s top mode s . crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 clock and reset [ clocks ] selectable from f ive clock sources ( 2 external oscillators, 2 built - in cr oscillator, and main pll) . ? main c lock: 4 mhz to 48 mhz ? sub clo ck : 32.768 k hz ? built - in high - speed cr clock : 4 mhz ? built - in low - speed cr clock : 100 k hz ? main pll clock [ resets ] ? reset requests from initx pin ? power - on reset ? software reset ? watchdog timers reset ? low - voltage detection reset ? clock s uper v isor reset clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? if e xternal clock failure (clock stop) is detected, reset is asserted. ? if e xternal frequency anomaly is detected, interrupt or reset is asserted.
document number: 002 - 05655 rev. *d page 4 of 101 mb9b120m series low - voltage detector (lvd) this series include 2 - stage monitoring of voltage on the vcc pins. when the voltage falls below the voltage that has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - p ower consumption mode six low - power consumption modes are supported. ? s leep ? t imer ? rtc ? s top ? deep s tandby rtc (selectable between keeping the value of ram and not ) ? deep standby stop (selectable between keeping the value of ram and not) debug serial wire jtag debug port (swj - dp) unique id unique value of the device (41 - bit) is set. power supply ? wide range voltage: vcc = 2.7 v t o 5.5 v
document number: 002 - 05655 rev. *d page 5 of 101 mb9b120m series contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 7 2. packages ................................ ................................ ................................ ................................ ................................ ........... 8 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 9 4. list of pin functions ................................ ................................ ................................ ................................ ....................... 15 5. i /o circuit type ................................ ................................ ................................ ................................ ................................ 31 6. handling precautions ................................ ................................ ................................ ................................ ..................... 38 6.1 precautions for product design ................................ ................................ ................................ ................................ ... 38 6.2 precautions for package mounting ................................ ................................ ................................ .............................. 39 6.3 precautions for use environment ................................ ................................ ................................ ................................ 40 7. handling devices ................................ ................................ ................................ ................................ ............................ 41 8. block diagram ................................ ................................ ................................ ................................ ................................ . 43 9. memory size ................................ ................................ ................................ ................................ ................................ .... 44 10. memory map ................................ ................................ ................................ ................................ ................................ .... 44 11. pin status in each cpu state ................................ ................................ ................................ ................................ ........ 47 12. electrical characteristics ................................ ................................ ................................ ................................ ............... 52 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 52 12.2 recommended operating conditions ................................ ................................ ................................ .......................... 54 12.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 55 12.3 .1 current rating ................................ ................................ ................................ ................................ .............................. 55 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 58 12.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 59 12.4.1 main clock input characteristics ................................ ................................ ................................ ................................ .. 59 12.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 60 12.4.3 built - in cr oscillation characteristics ................................ ................................ ................................ .......................... 60 12.4.4 operating conditions of main pll (in the case of using main clock for input of pll) ................................ .................. 61 12.4.5 operating conditions of main pll (in the case of using built - in high - speed cr for input clock of main pll) ......... 61 12.4.6 reset input characteristics ................................ ................................ ................................ ................................ .......... 62 12.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 62 12.4.8 base timer input timing ................................ ................................ ................................ ................................ .............. 63 12.4.9 csio/uart timing ................................ ................................ ................................ ................................ ...................... 64 12.4.10 external input timing ................................ ................................ ................................ ................................ ................ 72 12.4.11 quadrature position/revolution counter timing ................................ ................................ ................................ ........ 73 12.4.12 i 2 c timing ................................ ................................ ................................ ................................ ................................ . 75 12.4.13 jtag timing ................................ ................................ ................................ ................................ ............................. 76 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ .................... 77 12.6 10 - bit d/a converter ................................ ................................ ................................ ................................ .................... 80 12.7 low - voltage detection characteristics ................................ ................................ ................................ ........................ 81 12.7.1 low - voltage detection reset ................................ ................................ ................................ ................................ ....... 81 12.7.2 interrupt of low - voltage detection ................................ ................................ ................................ ............................... 82 12.8 flash memory write/erase characteristics ................................ ................................ ................................ ................. 83 12.8.1 write / erase time ................................ ................................ ................................ ................................ ......................... 83 12.8.2 write cycles and data hold time ................................ ................................ ................................ ................................ ... 83 12.9 return time from low - power consumption mode ................................ ................................ ................................ ...... 84 12.9.1 return factor: interrupt/wkup ................................ ................................ ................................ ................................ .... 84 12.9.2 return factor: reset ................................ ................................ ................................ ................................ .................... 86 13. ordering information ................................ ................................ ................................ ................................ ...................... 88 14. package dimensions ................................ ................................ ................................ ................................ ...................... 89
document number: 002 - 05655 rev. *d page 6 of 101 mb9b120m series 15. ma jor changes ................................ ................................ ................................ ................................ ................................ 97 document history ................................ ................................ ................................ ................................ ............................... 100 sales, solutions, and legal information ................................ ................................ ................................ ........................... 101
document number: 002 - 05655 rev. *d page 7 of 101 mb9b120m series 1. p roduct l ineup memory s ize product n ame mb9b f12 1 k / l / m mb9 bf122k/l/m mb9 bf124k/l/m on - chip flash memory main area 64 kbytes 128 kbytes 256 kbytes work area 32 kbytes 32 kbytes 32 kbytes on - chip sram sram0 8 kbytes 8 kbytes 16 kbytes sram1 8 kbytes 8 kbytes 16 kbytes total 16 kbytes 16 kbytes 32 kbytes function product n ame mb9bf121k mb9bf122k mb9bf124k mb9bf121l mb9bf122l mb9bf124l mb9bf121m mb9bf122m mb9bf124m pin count 48 64 80/96 cpu cortex - m 3 freq. 72 mhz power supply voltage range 2.7 v to 5 . 5 v dmac 8ch. multi - function serial interface (uart/csio/lin/i 2 c) 4 ch. (max) ch.0/1/3 : fifo ch.5 : no fifo (in ch. 1/ 5 , only uart and lin are available.) 8 ch. (max) ch .0/1/3/4 fifo ch .2/5/6/7 : no fifo (in ch. 1 , only uart and lin are available.) base timer (pwc/reload timer/pwm/ppg) 8ch. (max) mf timer a/d activation compare 2 ch. 1 unit input capture 4 ch. * free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 1 ch. 2 ch. (max) dual timer 1 unit real - time clock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 1 4 pin s (max) + nmi 1 19 pins (max) + nmi x 1 23 pins (max) + nmi x 1 i/o ports 35 pin s (max) 50 pin s (max) 60 pin s (max) 12 - bit a/d converter 14 ch. (2 unit s ) 23 ch. (2 unit s ) 26 ch. (2 unit s ) csv (clock super visor) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp unique id yes *: the external input channel which can be used is shown as foll o ws. ? ch.0 to ch.3: mb9bf121m/f122m/f124m ? ch.0, ch.2, ch.3: mb9bf121k/f122k/f124k, mb9bf121l/f122l/f124l note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. see 12 electrical characteristics 12.4 ac characteristics 12.4.3 built - in cr oscillation characteristics for the accuracy of the built - in cr.
document number: 002 - 05655 rev. *d page 8 of 101 mb9b120m series 2. packages product name package mb9bf 121k mb9bf122k mb9bf 124k mb9bf121l mb9bf122l mb9bf124l mb9bf121m mb9bf122m mb9bf124m lqfp: lqa048 (0.5 mm pitch) { - - qfn: vna048 (0.5 mm pitch) { - - lqfp: lqd064 (0.5 mm pitch) - { - lqfp: lqg064 (0.65 mm pitch) - { - qfp: vnc064 (0.5 mm pitch) - { - lqfp: lqh080 (0.5 mm pitch) - - { lqfp : lqj080 (0. 6 5 mm pitch) - - { bga: fdg096 (0.5 mm pitch) - - { { : supported note: see " package dimensions " for detailed information on each package
document number: 002 - 05655 rev. *d page 9 of 101 mb9b120m series 3. pin assignment lqh080 / lqj080 (top view) note: the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/int17_1 p80/int16_1 vcc p60/an21/sin5_0/tioa2_2/int15_1/wkup3/igtrg_1 p61/an20/sot5_0/tiob2_2/dtti0x_2 p62/an19/sck5_0/adtg_3 p63/int03_0 p0f/an18/nmix/subout_0/crout_1/rtcco_0/wkup0 p0e/cts4_0/tiob3_2/int21_0 p0d/rts4_0/tioa3_2/int20_0 p0c/an17/sck4_0/tioa6_1/int19_0 p0b/an16/sot4_0/tiob6_1/int18_0 p0a/an15/sin4_0/int00_2 p07/adtg_0/int23_1 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcc 1 60 p20/int05_0/crout_0/ain1_1 p50/an22/int00_0/ain0_2/sin3_1 2 59 p21/an14/sin0_0/int06_1/bin1_1/wkup2 p51/an23/int01_0/bin0_2/sot3_1 3 58 p22/an13/sot0_0/tiob7_1/zin1_1 p52/an24/int02_0/zin0_2/sck3_1 4 57 p23/an12/sck0_0/tioa7_1 p53/sin6_0/tioa1_2/int07_2 5 56 p1b/an11/sot4_1/int20_2/ic01_1 p54/sot6_0/tiob1_2/int18_1 6 55 p1a/an10/sin4_1/int05_1/ic00_1 p55/sck6_0/adtg_1/int19_1 7 54 p19/an09/sck2_2 p56/int08_2 8 53 p18/an08/sot2_2 p30/an25/ain0_0/tiob0_1/int03_2 9 52 avrl p31/an26/bin0_0/tiob1_1/sck6_1/int04_2 10 51 avrh p32/zin0_0/tiob2_1/sot6_1/int05_2 11 50 avcc p33/int04_0/tiob3_1/sin6_1/adtg_6 12 49 p17/an07/sin2_2/int04_1 p39/dtti0x_0/int06_0/adtg_2 13 48 p16/an06/sck0_1/int15_0 p3a/rto00_0/tioa0_1/int07_0/subout_2/rtcco_2 14 47 p15/an05/sot0_1/int14_0/ic03_2 p3b/rto01_0/tioa1_1 15 46 p14/an04/sin0_1/int03_1/ic02_2 p3c/rto02_0/tioa2_1/int18_2 16 45 avss p3d/rto03_0/tioa3_1 17 44 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa4_1/int19_2 18 43 p11/an01/sin1_1/int02_1/frck0_2/wkup1 p3f/rto05_0/tioa5_1 19 42 p10/an00 vss 20 41 vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p44/tioa4_0/int10_0 p45/tioa5_0/int11_0 c vss vcc p46/x0a p47/x1a initx p48/sin3_2/int14_1 p49/tiob0_0/sot3_2/int20_1/ain0_1/da0_0 p4a/tiob1_0/sck3_2/int21_1/bin0_1/da1_0 p4b/tiob2_0/int22_1/zin0_1/igtrg_0 p4c/tiob3_0/sck7_1/int12_0/ain1_2 p4d/tiob4_0/sot7_1/int13_0/bin1_2 p4e/tiob5_0/int06_2/sin7_1/zin1_2 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 80
document number: 002 - 05655 rev. *d page 10 of 101 mb9b120m series lqd064 / lqg064 (top view) note : the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr ) to select the pin. vss p81/int17_1 p80/int16_1 vcc p60/an21/sin5_0/tioa2_2/int15_1/wkup3/igtrg_1 p61/an20/sot5_0/tiob2_2/dtti0x_2 p62/an19/sck5_0/adtg_3 p0f/an18/nmix/subout_0/crout_1/rtcco_0/wkup0 p0c/an17/sck4_0/tioa6_1/int19_0 p0b/an16/sot4_0/tiob6_1/int18_0 p0a/an15/sin4_0/int00_2 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vcc 1 48 p21/an14/sin0_0/int06_1/wkup2 p50/an22/int00_0/ain0_2/sin3_1 2 47 p22/an13/sot0_0/tiob7_1 p51/an23/int01_0/bin0_2/sot3_1 3 46 p23/an12/sck0_0/tioa7_1 p52/an24/int02_0/zin0_2/sck3_1 4 45 p19/an09/sck2_2 p30/an25/ain0_0/tiob0_1/int03_2 5 44 p18/an08/sot2_2 p31/an26/bin0_0/tiob1_1/sck6_1/int04_2 6 43 avrl p32/zin0_0/tiob2_1/sot6_1/int05_2 7 42 avrh p33/int04_0/tiob3_1/sin6_1/adtg_6 8 41 avcc p39/dtti0x_0/int06_0/adtg_2 9 40 p17/an07/sin2_2/int04_1 p3a/rto00_0/tioa0_1/int07_0/subout_2/rtcco_2 10 39 p15/an05/sot0_1/int14_0/ic03_2 p3b/rto01_0/tioa1_1 11 38 p14/an04/sin0_1/int03_1/ic02_2 p3c/rto02_0/tioa2_1/int18_2 12 37 avss p3d/rto03_0/tioa3_1 13 36 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa4_1/int19_2 14 35 p11/an01/sin1_1/int02_1/frck0_2/wkup1 p3f/rto05_0/tioa5_1 15 34 p10/an00 vss 16 33 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c vcc p46/x0a p47/x1a initx p49/tiob0_0/sot3_2/int20_1/ain0_1/da0_0 p4a/tiob1_0/sck3_2/int21_1/bin0_1/da1_0 p4b/tiob2_0/int22_1/zin0_1/igtrg_0 p4c/tiob3_0/sck7_1/int12_0/ain1_2 p4d/tiob4_0/sot7_1/int13_0/bin1_2 p4e/tiob5_0/int06_2/sin7_1/zin1_2 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 64
document number: 002 - 05655 rev. *d page 11 of 101 mb9b120m series vnc064 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/int17_1 p80/int16_1 vcc p60/an21/sin5_0/tioa2_2/int15_1/wkup3/igtrg_1 p61/an20/sot5_0/tiob2_2/dtti0x_2 p62/an19/sck5_0/adtg_3 p0f/an18/nmix/subout_0/crout_1/rtcco_0/wkup0 p0c/an17/sck4_0/tioa6_1/int19_0 p0b/an16/sot4_0/tiob6_1/int18_0 p0a/an15/sin4_0/int00_2 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vcc 1 48 p21/an14/sin0_0/int06_1/wkup2 p50/an22/int00_0/ain0_2/sin3_1 2 47 p22/an13/sot0_0/tiob7_1 p51/an23/int01_0/bin0_2/sot3_1 3 46 p23/an12/sck0_0/tioa7_1 p52/an24/int02_0/zin0_2/sck3_1 4 45 p19/an09/sck2_2 p30/an25/ain0_0/tiob0_1/int03_2 5 44 p18/an08/sot2_2 p31/an26/bin0_0/tiob1_1/sck6_1/int04_2 6 43 avrl p32/zin0_0/tiob2_1/sot6_1/int05_2 7 42 avrh p33/int04_0/tiob3_1/sin6_1/adtg_6 8 41 avcc p39/dtti0x_0/int06_0/adtg_2 9 40 p17/an07/sin2_2/int04_1 p3a/rto00_0/tioa0_1/int07_0/subout_2/rtcco_2 10 39 p15/an05/sot0_1/int14_0/ic03_2 p3b/rto01_0/tioa1_1 11 38 p14/an04/sin0_1/int03_1/ic02_2 p3c/rto02_0/tioa2_1/int18_2 12 37 avss p3d/rto03_0/tioa3_1 13 36 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa4_1/int19_2 14 35 p11/an01/sin1_1/int02_1/frck0_2/wkup1 p3f/rto05_0/tioa5_1 15 34 p10/an00 vss 16 33 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c vcc p46/x0a p47/x1a initx p49/tiob0_0/sot3_2/int20_1/ain0_1/da0_0 p4a/tiob1_0/sck3_2/int21_1/bin0_1/da1_0 p4b/tiob2_0/int22_1/zin0_1/igtrg_0 p4c/tiob3_0/sck7_1/int12_0/ain1_2 p4d/tiob4_0/sot7_1/int13_0/bin1_2 p4e/tiob5_0/int06_2/sin7_1/zin1_2 pe0/md1 md0 pe2/x0 pe3/x1 vss qfn - 64
document number: 002 - 05655 rev. *d page 12 of 101 mb9b120m series lqa048 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin . vss p81/int17_1 p80/int16_1 vcc p60/an21/sin5_0/tioa2_2/int15_1/wkup3/igtrg_1 p61/an20/sot5_0/tiob2_2/dtti0x_2 p0f/an18/nmix/subout_0/crout_1/rtcco_0/wkup0 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 48 47 46 45 44 43 42 41 40 39 38 37 vcc 1 36 p21/an14/sin0_0/int06_1/wkup2 p50/an22/int00_0/ain0_2/sin3_1 2 35 p22/an13/sot0_0/tiob7_1 p51/an23/int01_0/bin0_2/sot3_1 3 34 p23/an12/sck0_0/tioa7_1 p52/an24/int02_0/zin0_2/sck3_1 4 33 avrl p39/dtti0x_0/int06_0/adtg_2 5 32 avrh p3a/rto00_0/tioa0_1/int07_0/subout_2/rtcco_2 6 31 avcc p3b/rto01_0/tioa1_1 7 30 p15/an05/sot0_1/int14_0/ic03_2 p3c/rto02_0/tioa2_1/int18_2 8 29 p14/an04/sin0_1/int03_1/ic02_2 p3d/rto03_0/tioa3_1 9 28 avss p3e/rto04_0/tioa4_1/int19_2 10 27 p12/an02/sot1_1/ic00_2 p3f/rto05_0/tioa5_1 11 26 p11/an01/sin1_1/int02_1/frck0_2/wkup1 vss 12 25 p10/an00 13 14 15 16 17 18 19 20 21 22 23 24 c vcc p46/x0a p47/x1a initx p49/tiob0_0/int20_1/da0_0 p4a/tiob1_0/int21_1/da1_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 48
document number: 002 - 05655 rev. *d page 13 of 101 mb9b120m series vna048 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/int17_1 p80/int16_1 vcc p60/an21/sin5_0/tioa2_2/int15_1/wkup3/igtrg_1 p61/an20/sot5_0/tiob2_2/dtti0x_2 p0f/an18/nmix/subout_0/crout_1/rtcco_0/wkup0 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 48 47 46 45 44 43 42 41 40 39 38 37 vcc 1 36 p21/an14/sin0_0/int06_1/wkup2 p50/an22/int00_0/ain0_2/sin3_1 2 35 p22/an13/sot0_0/tiob7_1 p51/an23/int01_0/bin0_2/sot3_1 3 34 p23/an12/sck0_0/tioa7_1 p52/an24/int02_0/zin0_2/sck3_1 4 33 avrl p39/dtti0x_0/int06_0/adtg_2 5 32 avrh p3a/rto00_0/tioa0_1/int07_0/subout_2/rtcco_2 6 31 avcc p3b/rto01_0/tioa1_1 7 30 p15/an05/sot0_1/int14_0/ic03_2 p3c/rto02_0/tioa2_1/int18_2 8 29 p14/an04/sin0_1/int03_1/ic02_2 p3d/rto03_0/tioa3_1 9 28 avss p3e/rto04_0/tioa4_1/int19_2 10 27 p12/an02/sot1_1/ic00_2 p3f/rto05_0/tioa5_1 11 26 p11/an01/sin1_1/int02_1/frck0_2/wkup1 vss 12 25 p10/an00 13 14 15 16 17 18 19 20 21 22 23 24 c vcc p46/x0a p47/x1a initx p49/tiob0_0/int20_1/da0_0 p4a/tiob1_0/int21_1/da1_0 pe0/md1 md0 pe2/x0 pe3/x1 vss qfn - 48
document number: 002 - 05655 rev. *d page 14 of 101 mb9b120m series fdg096 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. h j 11 a b c 6 7 k l d e f g 8 9 10 3 4 5 vcc p3d 1 2 vss vcc an22 p53 p3e vss an05 avss md1 vss x1a initx p4c p45 p49 p39 an25 an01 vss trstx vss p20 an12 an10 an07 vss p3f p56 vss p32 p3a vss p3b vss an11 an08 an06 an04 an02 an18 tck/ swclk vss p07 an16 tdo/ swo an17 an13 an15 an19 p81 p80 vcc vss tms/ swdio an24 an20 p63 p0d vss an26 vss an21 p0e p4e p48 p4a p4d md0 p55 x0 x1 vss index p33 p3c avcc an00 vcc vss c x0a vss p44 vss p4b an23 vss p54 vss tdi an14 vss an09 avrh avrl
document number: 002 - 05655 rev. *d page 15 of 101 mb9b120m series 4. list of pin functions list of pi n numbers the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function register ( epfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 1 b1 1 1 vcc - 2 c1 2 2 p50 f n int00_0 ain0_2 sin3_1 an22 3 c2 3 3 p51 f n int01_0 bin0_2 sot3_1 (sda3_1) an23 4 b3 4 4 p52 f n int02_0 zin0_2 sck3_1 (scl3_1) an24 5 d1 - - p53 e l sin6_0 tioa1_2 int07_2 6 d2 - - p54 e l sot6_0 (sda6_0) tiob1_2 int18_1 7 d3 - - p55 e l sck6_0 (scl6_0) adtg_1 int19_1 8 e1 - - p56 e l int08_2 9 e2 5 - p30 f n ain0_0 tiob0_1 int03_2 an25 10 e3 6 - p31 f n bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 an26
document number: 002 - 05655 rev. *d page 16 of 101 mb9b120m series pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 11 g1 7 - p32 e l zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 12 g2 8 - p33 e l int04_0 tiob3_1 sin6_1 adtg_6 13 g3 9 5 p39 e l dtti0x_0 int06_0 adtg_2 14 h1 10 6 p3a g l rto00_0 (ppg00_0) tioa0_1 int07_0 subout_2 rtcco_2 15 h2 11 7 p3b g k rto01_0 (ppg00_0) tioa1_1 16 h3 12 8 p3c g l rto02_0 (ppg02_0) tioa2_1 int18_2 17 j1 13 9 p3d g k rto03_0 (ppg02_0) tioa3_1 18 j2 14 10 p3e g l rto04_0 (ppg04_0) tioa4_1 int19_2 19 j4 15 11 p3f g k rto05_0 (ppg04_0) tioa5_1 20 l1 16 12 vss - 21 l5 - - p44 g l tioa4_0 int10_0 22 k5 - - p45 g l tioa5_0 int11_0
document number: 002 - 05655 rev. *d page 17 of 101 mb9b120m series pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 23 l2 17 13 c - 24 l4 - - vss - 25 k1 18 14 vcc - 26 l3 19 15 p46 d f x0a 27 k3 20 16 p47 d g x1a 28 k4 21 17 initx b c 29 j5 - - p48 e l int14_1 sin3_2 30 k6 22 18 p49 l l tiob0_0 int20_1 da0_0 - sot3_2 (sda3_2) ain0_1 31 j6 23 19 p4a l l tiob1_0 int21_1 da1_0 - sck3_2 (scl3_2) bin0_1 32 l7 24 - p4b e l tiob2_0 int22_1 igtrg_0 zin0_1 33 k7 25 - p4c i* l tiob3_0 sck7_1 (scl7_1) int12_0 ain1_2 34 j7 26 - p4d i* l tiob4_0 sot7_1 (sda7_1) int13_0 bin1_2 35 k8 27 - p4e i* l tiob5_0 int06_2 sin7_1 zin1_2 36 k9 28 20 md1 c e pe0 37 l8 29 21 md0 k d
document number: 002 - 05655 rev. *d page 18 of 101 mb9b120m series pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 38 l9 30 22 x0 a a pe2 39 l10 31 23 x1 a b pe3 40 l11 32 24 vss - 41 k11 33 - vcc - 42 j11 34 25 p10 f m an00 43 j10 35 26 p11 f n an01 sin1_1 int02_1 frck0_2 wkup1 4 4 j 8 3 6 2 7 p12 f m an02 sot1_1 (sda1_1) ic00_2 45 h10 37 28 avss - 46 h9 38 29 p14 f n an04 int03_1 ic02_2 sin0_1 47 g10 39 30 p15 f n an05 ic03_2 sot0_1 (sda0_1) int14_0 48 g9 - - p16 f n an06 sck0_1 (scl0_1) int15_0 49 f10 40 - p17 f n an07 sin2_2 int04_1 50 h11 41 31 avcc - 51 f11 42 32 avrh - 52 g11 43 33 av rl - 53 f9 44 - p18 f m an08 sot2_2 (sda2_2) 54 e11 45 - p19 f m an09 sck2_2 (scl2_2)
document number: 002 - 05655 rev. *d page 19 of 101 mb9b120m series pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 55 e10 - - p1a f n an10 sin4_1 int05_1 ic00_1 56 e9 - - p1b f n an11 sot4_1 (sda4_1) ic01_1 int20_2 57 d10 46 34 p23 f m sck0_0 (scl0_0) tioa7_1 an12 58 d9 47 35 p22 f m sot0_0 (sda0_0) tiob7_1 an13 - - zin1_1 59 c11 48 36 p21 f n sin0_0 int06_1 wkup2 bin1_1 an14 60 c10 - - p20 e n int05_0 crout _0 ain1_1 61 a10 49 37 p00 e j trstx 62 b9 50 38 p01 e j tck swclk 63 b11 51 39 p02 e j tdi 64 a9 52 40 p03 e j tms swdio 65 b8 53 41 p04 e j tdo swo 66 a8 - - p07 e l adtg_0 int23_1 67 c8 54 - p0a j* n sin4_0 int00_2 an15
document number: 002 - 05655 rev. *d page 20 of 101 mb9b120m series pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 68 c7 55 - p0b j* n sot4_0 (sda4_0) tiob6_1 an16 int18_0 69 b7 56 - p0c j* n sck4_0 (scl4_0) tioa6_1 int19_0 an17 70 b6 - - p0d e l rts4_0 tioa3_2 i nt20_0 71 c6 - - p0e e l cts4_0 tiob3_2 i nt21_0 72 a6 57 42 p0f f i nmix subout_0 crout_1 rtcco_0 wkup0 an18 73 b5 - - p63 e l int03_0 74 c5 58 - p62 f m sck5_0 (scl5_0) adtg_3 an19 75 b4 59 43 p61 f m sot5_0 (sda5_0) tiob2_2 dtti0x_2 an20 76 c4 60 44 p60 j* n sin5_0 tioa2_2 int15_1 wkup3 igtrg_1 an21
document number: 002 - 05655 rev. *d page 21 of 101 mb9b120m series pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 lqfp - 64 qfn - 64 lqfp - 48 qfn - 48 77 a4 61 45 vcc - 78 a3 62 46 p80 h h int16_1 79 a2 63 47 p81 h h int17_1 80 a1 64 48 vss - - a5, a7, a11, b2, b10, c3, c9, d11, f1, f2, f3, j3, j9, k2, k10, l6 - - vss - *: 5 v tolerant i/o
document number: 002 - 05655 rev. *d page 22 of 101 mb9b120m series list of functions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 adc adtg_0 a/d converter external trigger input pin 66 a8 - - adtg_1 7 d3 - - adtg_2 13 g3 9 5 adtg_3 74 c5 58 - adtg_6 12 g2 8 - an00 a/d converter analog input pin . anxx describes adc ch.xx . 42 j11 34 25 an01 43 j10 35 26 an02 44 j8 36 27 an04 46 h9 38 29 an05 47 g10 39 30 an06 48 g9 - - an07 49 f10 40 - an08 53 f9 44 - an09 54 e11 45 - an10 55 e10 - - an11 56 e9 - - an12 57 d10 46 34 an13 58 d9 47 35 an14 59 c11 48 36 an15 67 c8 54 - an16 68 c7 55 - an17 69 b7 56 - an18 72 a6 57 42 an19 74 c5 58 - an20 75 b4 59 43 an21 76 c4 60 44 an22 2 c1 2 2 an23 3 c2 3 3 an24 4 b3 4 4 an25 9 e2 5 - an26 10 e3 6 - base timer 0 tioa0_1 base timer ch.0 tioa pin 14 h1 10 6 tiob0_0 base timer ch.0 tiob pin 30 k6 22 18 tiob0_1 9 e2 5 - base timer 1 tioa1_1 base timer ch.1 tioa pin 15 h2 11 7 tioa1_2 5 d1 - - tiob1_0 base timer ch.1 tiob pin 31 j6 23 19 tiob1_1 10 e3 6 - tiob1_2 6 d2 - - base timer 2 tioa2_1 base timer ch.2 tioa pin 16 h3 12 8 tioa2_2 76 c4 60 44 tiob2_0 base timer ch.2 tiob pin 32 l7 24 - tiob2_1 11 g1 7 - tiob2_2 75 b4 59 43 base timer 3 tioa3_1 base timer ch.3 tioa pin 17 j1 13 9 tioa3_2 70 b6 - - tiob3_0 base timer ch.3 tiob pin 33 k7 25 - tiob3_1 12 g2 8 - tiob3_2 71 c6 - - base timer 4 tioa4_0 base timer ch.4 tioa pin 21 l5 - - tioa4_1 18 j2 14 10 tiob4_0 base timer ch.4 tiob pin 34 j7 26 -
document number: 002 - 05655 rev. *d page 23 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 base timer 5 tioa5_0 base timer ch.5 tioa pin 22 k5 - - tioa5_1 19 j4 15 11 tiob5_0 base timer ch.5 tiob pin 35 k8 27 - base timer 6 tioa6_1 base timer ch.6 tioa pin 69 b7 56 - tiob6_1 base timer ch.6 tiob pin 68 c7 55 - base timer 7 tioa7_1 base timer ch.7 tioa pin 57 d10 46 34 tiob7_1 base timer ch.7 tiob pin 58 d9 47 35 debugger swclk serial wire debug interface clock input pin 62 b9 50 38 swdio serial wire debug interface data input / output pin 64 a9 52 40 swo serial wire viewer output pin 65 b8 53 41 tck jtag test clock input pin 62 b9 50 38 tdi jtag test data input pin 63 b11 51 39 tdo jtag debug data output pin 65 b8 53 41 tms jtag test mode state input/output pin 64 a9 52 40 trstx jtag test reset i nput pin 61 a10 49 37
document number: 002 - 05655 rev. *d page 24 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 external interrupt int00_0 external interrupt request 00 input pin 2 c1 2 2 int00_2 67 c8 54 - int01_0 external interrupt request 0 1 input pin 3 c2 3 3 int02_0 external interrupt request 0 2 input pin 4 b3 4 4 int02_1 43 j10 35 26 int03_0 external interrupt request 0 3 input pin 73 b5 - - int03_1 46 h9 38 29 int03_2 9 e2 5 - int04_0 external interrupt request 04 input pin 12 g2 8 - int04_1 49 f10 40 - int04_2 10 e3 6 - int05_0 external interrupt request 0 5 input pin 60 p20 - - int05_1 55 e10 - - int05_2 11 g1 7 - int06_ 0 external interrupt request 0 6 input pin 13 g3 9 5 int06_1 59 c11 48 36 int06_2 35 k8 27 - int07_ 0 external interrupt request 0 7 input pin 14 h1 10 6 int07_2 5 d1 - - int08_2 external interrupt request 0 8 input pin 8 e1 - - int10_ 0 external interrupt request 10 input pin 21 l5 - - int11_ 0 external interrupt request 11 input pin 22 k5 - - int12_ 0 external interrupt request 12 input pin 33 k7 25 - int13_ 0 external interrupt request 13 input pin 34 j7 26 - int14_ 0 external interrupt request 14 input pin 47 g10 39 30 int14_1 29 j5 - - int15_ 0 external interrupt request 15 input pin 48 g9 - - int15_1 76 c4 60 44 int16_1 external interrupt request 16 input pin 78 a3 62 46 int17_1 external interrupt request 17 input pin 79 a2 63 47 int18_0 external interrupt request 18 input pin 68 c7 55 - int18_1 6 d2 - - int18_2 16 h3 12 8 int19_0 external interrupt request 19 input pin 59 c11 56 - int19_1 7 d3 - - int19_2 18 j2 14 10 int20_0 external interrupt request 20 input pin 70 b6 - - int20_1 30 k6 22 18 int20_2 56 e9 - - int21_0 external interrupt request 21 input pin 71 c6 - - int21_1 31 j6 23 19 int22_1 external interrupt request 22 input pin 32 l7 24 - int23_1 external interrupt request 23 input pin 66 a8 - - nmix non - maskable interrupt input pin 72 a6 57 42
document number: 002 - 05655 rev. *d page 25 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 gpio p00 general - purpose i/o port 0 61 a10 49 37 p01 62 b9 50 38 p02 63 b11 51 39 p03 64 a9 52 40 p04 65 b8 53 41 p07 66 a8 - - p0a 67 c8 54 - p0b 68 c7 55 - p0c 69 b7 56 - p0d 70 b6 - - p0e 71 c6 - - p0f 72 a6 57 42 p10 general - purpose i/o port 1 42 j11 34 25 p11 43 j10 35 26 p12 44 j8 36 27 p14 46 h9 38 29 p15 47 g10 39 30 p16 48 g9 - - p17 49 f10 40 - p18 53 f9 44 - p19 54 e11 45 - p1a 55 e10 - - p1b 56 e9 - - p20 general - purpose i/o port 2 60 c10 - - p21 59 c11 48 36 p22 58 d9 47 35 p23 57 d10 46 34 p30 general - purpose i/o port 3 9 e2 5 - p31 10 e3 6 - p32 11 g1 7 - p33 12 g2 8 - p39 13 g3 9 5 p3a 14 h1 10 6 p3b 15 h2 11 7 p3c 16 h3 12 8 p3d 17 j1 13 9 p3e 18 j2 14 10 p3f 19 j4 15 11
document number: 002 - 05655 rev. *d page 26 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 gpio p44 general - purpose i/o port 4 21 l5 - - p45 22 k5 - - p46 26 l3 19 15 p47 27 k3 20 16 p48 29 j5 - - p49 30 k6 22 18 p4a 31 j6 23 19 p4b 32 l7 24 - p4c 33 k7 25 - p4d 34 j7 26 - p4e 35 k8 27 - p50 general - purpose i/o port 5 2 c1 2 2 p51 3 c2 3 3 p52 4 b3 4 4 p53 5 d1 - - p54 6 d2 - - p55 7 d3 - - p56 8 e1 - - p60 general - purpose i/o port 6 76 c4 60 44 p61 75 b4 59 43 p62 74 c5 58 - p63 73 b5 - - p80 general - purpose i/o port 8 78 a3 62 46 p81 79 a2 63 47 pe0 general - purpose i/o port e 36 k9 28 20 pe2 38 l9 30 22 pe3 39 l10 31 23 multi - function serial 0 sin0_0 multi - function serial interface ch.0 input pin 59 c11 48 36 sin0_1 46 h9 38 29 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 58 d9 47 35 sot0_1 (sda0_1) 47 g10 39 30 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a csio (operation mode 2) and as scl0 when it is used in an i 2 c (operation mode 4). 57 d10 46 34 sck0_1 (scl0_1) 48 g9 - - multi - function serial 1 sin1_1 multi - function serial interface ch.1 input pin 43 j10 35 26 sot1_1 (sda1_1) multi - function serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/ lin (operation modes 0 ,1,3 ) . 44 j8 36 27 multi - function serial 2 sin2_ 2 multi - function serial interface ch.2 input pin 49 f10 40 - sot2_ 2 (sda2_ 2 ) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). 53 f9 44 - sck2_ 2 (scl2_ 2 ) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a csio (operation mode 2 ) and as scl2 when it is used in an i 2 c (operation mode 4). 54 e11 45 -
document number: 002 - 05655 rev. *d page 27 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 multi - function serial 3 sin3_ 1 multi - function serial interface ch.3 input pin 2 c1 2 2 sin3_ 2 29 j5 - - sot3_ 1 (sda3_ 1 ) multi - function serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). 3 c2 3 3 sot3_ 2 (sda3_ 2 ) 30 k6 - - sck3_ 1 (scl3_ 1 ) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a csio (operation mode 2) and as scl3 when it is used in an i 2 c (operation mode 4). 4 b3 4 4 sck3_ 2 (scl3_ 2 ) 31 j6 - - multi - function serial 4 sin4_0 multi - function serial interface ch.4 input pin 67 c8 54 - sin4_1 55 e10 - - sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda4 when it is used in an i 2 c (operation mode 4). 68 c7 55 - sot4_1 (sda4_1) 56 e9 - - sck4_0 (scl4_0) multi - function serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a csio (operation mode 2) and as scl4 when it is used in an i 2 c (operation mode 4). 69 b7 56 - rts4_0 multi - function serial interface ch.4 rts output pin 70 b6 - - cts4_0 multi - function serial interface ch.4 cts input pin 71 c6 - - multi - function serial 5 sin5_0 multi - function serial interface ch.5 input pin 76 c4 60 44 sot5_0 (sda5_0) multi - function serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 75 b4 59 43 sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a csio (operation mode 2 ) and as scl5 when it is used in an i 2 c (operation mode 4). 74 c5 58 -
document number: 002 - 05655 rev. *d page 28 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 multi - function serial 6 sin6_0 multi - function serial interface ch.6 input pin 5 d1 - - sin6_1 12 g2 8 - sot6_0 (sda6_0) multi - function serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 6 d2 - - sot6_1 (sda6_1) 11 g1 7 - sck6_0 (scl6_0) multi - function serial interface ch. 6 clock i/o pin. this pin operates as sck 6 when it is used in a csio (operation mode 2) and as scl 6 when it is used in an i 2 c (operation mode 4). 7 d3 - - sck6_1 (scl6_1) 10 e3 6 - multi - function serial 7 sin7_ 1 multi - function serial interface ch. 7 input pin 35 k8 27 - sot7_ 1 (sda7_ 1 ) multi - function serial interface ch. 7 output pin. this pin operates as sot 7 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 7 when it is used in an i 2 c (operation mode 4). 34 j7 26 - sck7_ 1 (scl7_ 1 ) multi - function serial interface ch. 7 clock i/o pin. this pin operates as sck 7 when it is used in a csio (operation mode 2) and as scl 7 when it is used in an i 2 c (operation mode 4). 33 k7 25 -
document number: 002 - 05655 rev. *d page 29 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 multi - function timer 0 dtti0x_0 input signal of waveform generator to control outputs rto00 to rto05 of multi - function timer 0. 13 g3 9 5 dtti0x_2 75 b4 59 43 frck0_ 2 16 - bit free - run timer ch.0 external clock input pin 43 j10 35 26 ic00_1 16 - bit input capture input pin of multi - function timer 0 . icxx describes chan n el number. 55 e10 - - ic00_ 2 44 j8 36 27 ic01_1 56 e9 - - ic02_ 2 46 h9 38 29 ic03_ 2 47 g10 39 30 rto00_0 (ppg00_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode . 14 h1 10 6 rto01_0 (ppg00_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode . 15 h2 11 7 rto02_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode . 16 h3 12 8 rto03_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode . 17 j1 13 9 rto04_0 (ppg04_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode . 18 j2 14 10 rto05_0 (ppg04_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode . 19 j4 15 11 igtrg_0 ppg igbt mode external trigger input pin 32 l7 24 - igtrg_1 76 c4 60 44 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 9 e2 5 - ain0_1 30 k6 22 - ain0_2 2 c1 2 2 bin0_0 qprc ch.0 bin input pin 10 e3 6 - bin0_1 31 j6 23 - bin0_2 3 c2 3 3 zin0_0 qprc ch.0 zin input pin 11 g1 7 - zin0_1 32 l7 24 - zin0_2 4 b3 4 4 quadrature position/ revolution counter 1 ain1_1 qprc ch.1 ain input pin 60 c10 - - ain1_2 33 k7 25 - bin1_1 qprc ch.1 bin input pin 59 c11 - - bin1_2 34 j7 26 - zin1_1 qprc ch.1 zin input pin 58 d9 - - zin1_2 35 k8 27 - real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 72 a6 57 42 rtcco_2 14 h1 10 6 subout_0 sub clock output pin 72 a6 57 42 subout_2 14 h1 10 6
document number: 002 - 05655 rev. *d page 30 of 101 mb9b120m series pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 low - power consumption mode wkup0 deep standby mode return signal input pin 0 72 a6 57 42 wkup1 deep standby mode return signal input pin 1 43 j10 35 26 wkup2 deep standby mode return signal input pin 2 59 c11 48 36 wkup3 deep standby mode return signal input pin 3 76 c4 60 44 dac da0 d/a converter ch.0 analog output pin 30 k6 22 18 da1 d/a converter ch.1 analog output pin 31 j6 23 19 r eset initx external reset input pin. a reset is valid when initx="l". 28 k4 21 17 mode md0 mode 0 pin. during normal operation, md0="l" must be input. during serial programming to f lash memory, md0="h" must be input. 37 l8 29 21 md1 mode 1 pin. during serial programming to f lash memory, md1="l" must be input. 36 k9 28 20 p ower vcc power supply pin 1 b1 1 1 vcc power supply pin 25 k1 18 14 vcc power supply pin 41 k11 33 - vcc power supply pin 77 a4 61 45 gnd vss gnd pin - f1 - - vss gnd pin - f2 - - vss gnd pin - f3 - - vss gnd pin - b2 - - vss gnd pin 20 l1 16 12 vss gnd pin - k2 - - vss gnd pin - j3 - - vss gnd pin - l6 - - vss gnd pin 24 l4 - - vss gnd pin 40 l11 32 24 vss gnd pin - k10 - - vss gnd pin - j9 - - vss gnd pin - b10 - - vss gnd pin - c9 - - vss gnd pin - d11 - - vss gnd pin - a11 - - vss gnd pin - a7 - - vss gnd pin - c3 - - vss gnd pin - a5 - - vss gnd pin 80 a1 64 48 c lock x0 main clock (oscillation) input pin 38 l9 30 22 x0a sub clock (oscillation) input pin 26 l3 19 15 x1 main clock (oscillation) i/o pin 39 l10 31 23 x1a sub clock (oscillation) i/o pin 27 k3 20 16 crout _0 built - in high - speed cr - osc clock output port 60 c10 - - crout _1 72 a6 57 42 analog p ower avcc a/d converter and d/a converter analog power supply pin 50 h11 41 31 avrh a/d converter analog reference voltage input pin 51 f11 42 32 analog gnd avss a/d converter and d/a converter gnd pin 45 h10 37 28 avrl a/d converter analog reference voltage input pin 52 g11 43 33 c pin c power supply stabilization capacity pin 23 l2 17 13 note: while this device contains a test access port (tap) based on the ieee 1149.1 - 2001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other devices with differe nt functionality. the tap pins may also be configurable for purposes other than access to the tap controller.
document number: 002 - 05655 rev. *d page 31 of 101 mb9b120m series 5. i / o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor $ssur[lpdwho\0 ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor $ssur[lpdwho\n ? i oh = - 4 ma , i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control
document number: 002 - 05655 rev. *d page 32 of 101 mb9b120m series type circuit remarks b ? cmos level hysteresis input ? pull - up resistor $ssur[lpdwho\n c ? open drain output ? cmos level hysteresis input pull - up resistor digital in put digital input digital out put n-ch
document number: 002 - 05655 rev. *d page 33 of 101 mb9b120m series type circuit remarks d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 0 ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control
document number: 002 - 05655 rev. *d page 34 of 101 mb9b120m series type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 05655 rev. *d page 35 of 101 mb9b120m series type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 18 ma, i ol = 16.5 ma digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output digital input standby mode c ontrol p-ch p-ch n-ch r p-ch n-ch r
document number: 002 - 05655 rev. *d page 36 of 101 mb9b120m series type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5 v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off j ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? 5 v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off k ? cmos level hysteresis input digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control mode input p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 05655 rev. *d page 37 of 101 mb9b120m series type circuit remarks l ? cmos level output ? cmos level hysteresis input ? with input control ? analog output ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 n ? i oh = - 4 ma, i ol = 4 ma p - c h p - c h n - c h a n a l o g o u t p u t r d i g i t a l o u t p u t d i g i t a l o u t p u t d i g i t a l i n p u t s t a n d b y m o d e c o n t r o l p u l l - u p r e s i s t o r c o n t r o l
document number: 002 - 05655 rev. *d page 38 of 101 mb9b120m series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the condit ions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be obs erved to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices . 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute ma ximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended opera ting conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of p ins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum rat ings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output p ins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pin s unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in exce ss of several hundred ma to flow continuous ly at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happenin g, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observ ance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from suc h failures by incorporating safety design measures into your facility and equipment such a s redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions.
document number: 002 - 05655 rev. *d page 39 of 101 mb9b120m series precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the u se of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (s uch as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior app roval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress ? recommended conditions. for detailed information a bout mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting ont o boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be s ubjected to thermal str ess in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead - inserti on packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connec tions caused by deformed pins, or shorting due to solder bridges. you mu st use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. le ad - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reduci ng moisture resistance and causi ng packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. produ cts should be stored below 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125c/24 h
document number: 002 - 05655 rev. *d page 40 of 101 mb9b120m series static electricity because semiconductor devices are particularly susceptible to damage by sta tic electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vesse ls, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats an d other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 6.3 precautions fo r use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke , flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in oth er special environmental conditions should consult with sales representatives.
document number: 002 - 05655 rev. *d page 41 of 101 mb9b120m series 7. handling devices power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the groun d level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connect ed as a bypass capacitor between each power supply pin and gnd pin, between avcc pin and avss pin, between avrh pin and avrl pin near this device. stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly eve n though the fluctuation is within the recommended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple ( peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc ydoxhlqwkhuhfrpphqghgrshudwlqjfrqglwlrqvdqgwkhwudqvlhqwioxfwxdwlrqudwhgrhvqrwh[fhhg9vzkhqwkhuhlvd momentary fluctuation on switching the power supply. crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the devi ce as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ? surface mount type size : more than 3.2 mm 1.5 mm load capacitance : approximately 6 pf to 7 pf ? lead type load capacitance : approximately 6 pf to 7 pf using an external clock when using an external cloc k as an input of the main clock , set x0 / x1 to the external clock input, and input the clock to x0 . x1 (pe3) can be used as a general - purpose i/o port. similarly, w hen using an external cloc k as an input of the sub clock , set x0 a/ x1 a to the external clock input, and input the clock to x0 a. x1 a (p47) can be used as a general - purpose i/o port. ?
document number: 002 - 05655 rev. *d page 42 of 101 mb9b120m series handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disable d . however, i 2 c pins need to keep the electrical char acteristic like other pins and not to connect to the external i 2 c bus system with power off. c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceramic c apacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the d evice erroneously switching to test mode due to noise. notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter and d/a converter , connect avcc = vcc and avss = vss. turning on : 9&&: avcc : avrh turning off : avrh : avcc : vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving w rong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. differences in features among the products with different memory sizes and between flash memory products and ma sk products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash memory products and mask products are different bec ause chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i / o. device c vss c s gnd
document number: 002 - 05655 rev. *d page 43 of 101 mb9b120m series 8. block diagram m b 9 b f 1 2 1 k / l / m , f 1 2 2 k / l / m , f 1 2 4 k / l / m c o r t e x - m 3 t r s t x , t c k , t d i , t m s a v c c , a v s s , a v r h , a v r l a n x x t i o a x t i o b x c t d o s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , ? ? ? p f x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r c r c a c c e l e r a t o r a d t g x r t s 4 c t s 4 o n - c h i p f l a s h 6 4 + 3 2 k b y t e s / 1 2 8 + 3 2 k b y t e s / 2 5 6 + 3 2 k b y t e s m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 0 / 1 / 3 / 4 ) h w f l o w c o n t r o l ( c h . 4 ) g p i o p i n - f u n c t i o n - c t r l l v d r o m t a b l e s w j - d p l v d c t r l b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . r e a l - t i m e c o l c k r t c c o _ x , s u b o u t _ x d e e p s t a n d b y c t r l w k u p x u n i t 0 u n i t 1 1 0 - b i t d / a c o n v e r t e r 2 u n i t s d a x q p r c 2 c h . a i n x b i n x z i n x m u l t i - f u n c t i o n t i m e r 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 2 c h . 1 6 - b i t p p g 3 c h . i c 0 x d t t i 0 x r t o 0 x f r c k x i g t r g _ x a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) a h b - a h b b r i d g e m u l t i - l a y e r a h b ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z ) x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z x 1 a
document number: 002 - 05655 rev. *d page 44 of 101 mb9b120m series 9. memory size see " memory size " in "product lineup" to confirm the memory size. 10. memory map memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0xe000_0000 0x4006_1000 0x4006_0000 dmac 0x4003_c000 0x4003_b000 rtc 0x7000_0000 0x4003_a000 watch counter 0x4003_9000 crc 0x6000_0000 0x4003_8000 mfs 0x4003_6000 0x4400_0000 0x4003_5000 lvd/ds mode 0x4003_4000 reserved 0x4200_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4000_0000 0x4003_1000 int-req.read 0x4003_0000 exti 0x2400_0000 0x4002_f000 reserved 0x4002_e000 cr trim 0x2200_0000 0x4002_9000 reserved 0x4002_8000 d/ac 0x2008_0000 0x4002_7000 a/dc 0x2000_0000 sram1 0x4002_6000 qprc 0x1ff8_0000 sram0 0x4002_5000 base timer 0x4002_4000 ppg 0x0020_8000 0x0020_0000 flash(work area) 0x0010_4000 reserved 0x4002_1000 0x0010_0000 security/cr trim 0x4002_0000 mft unit0 0x4001_6000 0x4001_5000 dual timer 0x4001_3000 0x0000_0000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f see " ?
document number: 002 - 05655 rev. *d page 45 of 101 mb9b120m series memory map (2) r efer to the programming manual for the detail of flash main area. ? mb9ab40n/a40n/340n/140n/150r,mb9b520m/320m/120m series flash programming manual mb9bf124k/l/m mb9bf122k/l/m mb9bf121k/l/m 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_e000 0x1fff_e000 0x1fff_c000 0x0020_8000 0x0020_8000 0x0020_8000 sa7(8kb) sa7(8kb) sa7(8kb) sa6(8kb) sa6(8kb) sa6(8kb) sa5(8kb) sa5(8kb) sa5(8kb) 0x0020_0000 sa4(8kb) 0x0020_0000 sa4(8kb) 0x0020_0000 sa4(8kb) 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x0004_0000 0x0002_0000 0x0001_0000 sa3(8kb) sa3(8kb) sa3(8kb) 0x0000_0000 sa2(8kb) 0x0000_0000 sa2(8kb) 0x0000_0000 sa2(8kb) flash(main area) 64kbytes sa8(48kb) sa8(48kb) sa8(48kb) reserved reserved sa11(64kb) flash(main area) 256kbytes sa10(64kb) sa9(64kb) sa9(64kb) flash(main area) 128kbytes flash(work area) 32kbytes reserved reserved reserved reserved sram1 8kbytes sram1 8kbytes sram0 8kbytes sram0 8kbytes reserved reserved flash(work area) 32kbytes sram0 16kbytes sram1 16kbytes reserved reserved reserved flash(work area) 32kbytes reserved
document number: 002 - 05655 rev. *d page 46 of 101 mb9b120m series peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_ 3 fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter (qprc) 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_8 fff d /a converter 0x4002_ 9 000 0x4002_dfff reserved 0x4002_e000 0x4002_efff b uilt - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt 0x4003_1000 0x4003_1fff interrupt source check register 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5 7 ff low - voltage detector 0x4003_ 58 00 0x4003_5 f ff deep standby mode controller 0x4003_ 6 000 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_ f fff reserved 0x4004_0000 0x400 5 _ffff ahb reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_ 1 000 0x41ff_ffff reserved
document number: 002 - 05655 rev. *d page 47 of 101 mb9b120m series 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the " l " level. ? initx=1 this is the period when the initx pin is the " h " level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 0 " . ? spl=1 this is the status that the standby pin level setting bit (spl ) in the standby mode control register (stb_ctl) is set to " 1 " . ? input enabled indicates that the input function can be used. ? internal input fixed at " 0 " this is the status that the input function cannot be used. internal input is fixed at " l " . ? hi - z indicat es that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in p eripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. ? gpio selected in deep standby mode, pins switch to the general - purpose i/o port.
document number: 002 - 05655 rev. *d page 48 of 101 mb9b120m series list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state main crystal oscillator output pin hi - z / internal input fixed at "0"/ or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state/ when oscillation stops*1, hi - z / internal input fixed at "0" maintain previous state/ when oscillation stops*1, hi - z / internal input fixed at "0" maintain previous state/ when oscillation stops*1, hi - z / internal input fixed at "0" maintain previous state/ when oscill ation stops*1, hi - z / internal input fixed at "0" maintain previous state/ when oscillation stops*1, hi - z / internal input fixed at "0" maintain previous state/ when oscillation stops*1, hi - z / internal input fixed at "0" c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled
document number: 002 - 05655 rev. *d page 49 of 101 mb9b120m series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / input enabled gpio selected hi - z / input enabled gpio selected f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled g gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state sub crystal oscillator output pin hi - z / internal input fixed at " 0 " / or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" h external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0"
document number: 002 - 05655 rev. *d page 50 of 101 mb9b120m series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ \ \ \ \
document number: 002 - 05655 rev. *d page 51 of 101 mb9b120m series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ \ \ \ \
document number: 002 - 05655 rev. *d page 52 of 101 mb9b120m series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1, * 2 v cc v ss - 0.5 v ss + 6.5 v analog power supply voltage * 1, * 3 av cc v ss - 0.5 v ss + 6.5 v analog reference voltage * 1, * 3 avrh v ss - 0.5 v ss + 6.5 v input voltage * 1 v i v ss - 0.5 v cc + 0.5 ( ? 6.5 v ) v v ss - 0.5 v ss + 6.5 v 5v tolerant analog pin input voltage * 1 v ia v ss - 0.5 av cc + 0.5 ( ? 6.5 v ) v output voltage * 1 v o v ss - 0.5 v cc + 0.5 ( ? 6.5 v ) v clamp maximum current i clamp - 2 +2 ma *7 clamp total maximum current ? [i clamp ] +20 ma *7 " l " level maximum output current * 4 i ol - 10 ma 4ma type 20 ma 12 ma type 39 ma p80/p81 pin " l " level average output current * 5 i olav - 4 ma 4ma type 12 ma 12ma type 16.5 ma p80/p81 pin " l " level total maximum output current ? i ol - 100 ma " l " level total maximum output current * 8 ? i olav - 50 ma " h " level maximum output current * 6 i oh - - 10 ma 4ma type - 20 ma 12 ma type - 39 ma p80/p81 pin " h " level average output current * 7 i ohav - - 4 ma 4ma type - 12 ma 12 ma type - 1 8 ma p80/p81 pin " h " level total maximum output current ? i oh - - 100 ma " h " level total average output current * 8 ? i ohav - - 50 ma power consumption p d - 300 mw storage temperature t stg - 55 + 150 c *1 : these parameters are based on the condition that v ss = av ss = 0 v. *2 : v cc must not drop below v ss - 0.5 v. *3 : ensure that the voltage does not exceed v cc + 0. 5 v, for example, when the power is turned on. *4 : the maximum output current is defined as the value of the peak current flowing through any one of the corres ponding pins . *5 : the average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6 : the total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms period.
document number: 002 - 05655 rev. *d page 53 of 101 mb9b120m series * 7 : ? see " list of pin functions " and " i / o circuit type " about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consump t ion modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is o ff (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example (i/o equivalent circuit ) . warning : semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. r +b input (0v to 16v) p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output protection diode
document number: 002 - 05655 rev. *d page 54 of 101 mb9b120m series 12.2 recommended operating conditions (v ss = av ss = avrl = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc - 2.7 * 2 5.5 v analog power supply voltage av cc - 2.7 5.5 v av cc = v cc analog reference voltage avrh - 2.7 av cc v avrl av ss av ss v smoothing capacitor c s - 1 10 ) for regulator* 1 operating temperature t a - - 40 + 105 c * 1 : see "c pin" in " handling devices " for the connection of the smoothing capacitor. * 2 : in between less than the minimum power supply voltage and low voltage reset/interrupt detection volta ge or more, instruction execution and low voltage detection function by built - in high - speed cr (inc luding main pll is used) or bu ilt - in low - speed cr is possible to operate only . warning : the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 05655 rev. *d page 55 of 101 mb9b120m series 12.3 dc characteristics 12.3.1 current rating (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks typ max r un mode current i cc vcc pll r un mode cpu: 72 mhz , peripheral: 36 mhz 32.5 41 ma *1 , *5 cpu:72 mhz, peripheral clock stops nop operation 18 23 ma *1 , *5 high - speed cr r un mode cpu/ peripheral: 4 mhz* 2 2.5 3.4 ma *1 sub r un mode cpu/ peripheral: 32 khz 110 980 a *1 , * 6 low - speed cr r un mode cpu/ peripheral: 100 khz 130 1030 a *1 s leep mode current i ccs pll s leep mode peripheral: 36 mhz 22 28 ma *1 , *5 high - speed cr s leep mode peripheral: 4 mhz* 2 1.6 2.6 ma *1 sub s leep mode peripheral: 32 khz 96 955 a *1 , * 6 low - speed cr s leep mode peripheral: 100 khz 115 975 a *1 *1: when a l l ports are fixed. *2: when setting it to 4 mhz by trimming. * 3 : t a =+25c, v cc = 5.5 v * 4 : t a =+ 105 c, v cc =5.5 v *5: when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit )
document number: 002 - 05655 rev. *d page 56 of 101 mb9b120m series (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks typ * 2 max * 2 timer mode current i cc t vcc main timer mode t a = + 25 c , when lvd is off 4.1 4.8 m a *1 , * 4 t a = + 105 c , when lvd is off - 5.4 m a *1 , * 4 i cc t sub timer mode t a = + 25 c , when lvd is off 17 66 a *1 , *5 t a = + 105 c , when lvd is off - 835 a *1 , *5 rtc mode current i cc r rtc mode t a = + 25 c , when lvd is off 15 61 a *1 , *5 t a = + 105 c , when lvd is off - 680 a *1 , *5 stop mode current i cc h stop mode t a = + 25 c , when lvd is off 14 53 a *1 t a = + 105 c , when lvd is off - 600 a *1 deep standby mode current i cc rd deep standby rtc mode t a = + 25 c , when lvd is off , when ram is off 2.2 11 a *1 , *3, *5 t a = + 25 c , when lvd is off , when ram is on 6.2 23 a *1 , *3, *5 t a = + 105 c , when lvd is off , when ram is off - 155 a *1 , *3, *5 t a = + 105 c , when lvd is off , when ram is on 215 a *1 , *3, *5 i cc h d deep standby stop mode t a = + 25 c , when lvd is off , when ram is off 1.6 9.6 a *1 , *3 t a = + 25 c , when lvd is off , when ram is on 5.6 22 a *1 , *3 t a = + 105 c , when lvd is off , when ram is off - 150 a *1 , *3 t a = + 105 c , when lvd is off , when ram is on 210 a *1 , *3 *1: when a l l ports are fixed. * 2 : v cc =5.5 v *3: ram on/off setting is on - chip sram only. *4: when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit ) * 5 : when using the crystal oscillator of 32 khz (including the curre nt consumption of the oscillation circuit )
document number: 002 - 05655 rev. *d page 57 of 101 mb9b120m series low - v oltage d etection current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cc lvd vcc at operation for reset vcc = 5.5 v 0.13 0.3 a at not detect at operation for interrupt vcc = 5.5 v 0.13 0.3 a at not detect flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 9.5 11.2 ma * *: the current at which to write or erase flash memory, " i ccflash " is added to " i cc " . a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.69 0.90 ma at stop 0.25 25.84 a reference power supply current i ccavrh avrh at 1unit operation avrh=5.5 v 1.1 1.97 ma at stop 0.2 3.4 a d/a converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks min typ max power supply current * 1 i dda * 2 avcc at 1unit operation av cc =3.3 v 250 315 380 a at 1unit operation av cc =5.0 v 380 475 580 a i dsa at stop - - 16 a *1: no - load *2: generates the max current by the code about 0x200
document number: 002 - 05655 rev. *d page 58 of 101 mb9b120m series 12.3.2 pin characteristics (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin , md0 , md1 - v cc 0.8 - v cc + 0.3 v 5v tolerant input pin - v cc 0.8 - v ss + 5.5 v l level input voltage (hysteresis input) v ils cmos hysteresis input pin , md0 , md1 - v ss - 0.3 - v cc 0.2 v 5 v tolerant input pin - v ss - 0.3 - v cc 0.2 v h level output voltage v oh 4 ma type v cc ? 4.5 v , i oh = - 4 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 2 ma 12 ma type v cc ? 4.5 v , i oh = - 12 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 8 ma p80, p81 v cc ? 4.5 v , i oh = - 18.0 ma v cc - 0.4 - v cc v v cc < 4.5 v , i oh = - 12.0 ma l level output voltage v ol 4 ma type v cc ? 4.5 v , i ol = 4 ma v ss - 0.4 v v cc < 4.5 v , i ol = 2 ma 12 ma type v cc ? 4.5 v , i ol = 12 ma v ss - 0.4 v v cc < 4.5 v , i ol = 8 ma p80, p81 v cc ? 4.5 v , i ol = 16.5 ma v ss - 0.4 v v cc < 4.5 v , i ol = 10.5 ma input leak current i il - - - 5 - + 5 a pull - up resistance value r pu pull - up pin v cc ? 4.5 v 33 50 90 k v cc < 4.5 v - - 180 input capacitance c in other than vcc, vss, avcc, avss, avrh , avrl - - 5 15 pf
document number: 002 - 05655 rev. *d page 59 of 101 mb9b120m series 12.4 ac characteristics 12.4.1 main clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 10 5 c) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 , x1 v cc ? 4.5 v 4 48 mhz when crystal oscillator is connected v cc < 4.5 v 4 20 v cc ? 4.5 v 4 48 mhz when using external clock v cc < 4.5 v 4 20 input clock cycle t cylh v cc ? 4.5 v 20.83 250 ns when using external clock v cc < 4.5 v 50 250 input clock pulse width - p wh /t cylh , p wl /t cylh 45 55 % when using external clock input clock rising time and falling time t cf, t cr - - 5 ns when using external clock internal operating clock frequency * 1 f cm - - - 72 mhz master clock f cc - - - 72 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock* 2 f cp1 - - - 40 mhz apb1 bus clock* 2 f cp2 - - - 40 mhz apb2 bus clock* 2 internal operating clock cycle time * 1 t cycc - - 13.8 - ns base clock (hclk/fclk) t cycp0 - - 25 - ns apb0 bus clock * 2 t cycp1 - - 25 - ns apb1 bus clock * 2 t cycp2 - - 25 - ns apb2 bus clock * 2 *1: for more information about each internal operating clock , see " chapter 2 - 1 : clock " in " fm3 family peripheral manual ". *2: for about each apb bus which each peripheral is connected to , see " block diagram " in this data sheet. x0
document number: 002 - 05655 rev. *d page 60 of 101 mb9b120m series 12.4.2 sub clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/ t cyll x0a , x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - p wh /t cyll , p wl /t cyll 45 - 55 % when using external clock *: see " s ub crystal oscillator " in " handling devices " for the crystal oscillator used . 12.4.3 built - in cr oscillation characteristics built - in high - speed cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c 3.9 2 4 4.0 8 mhz when trimming * 1 t a = 0 c to + 8 5 c 3.9 4 4.1 t a = - 4 0 c to + 10 5 c 3.88 4 4.12 t a = + 25 c v cc ? 3.6 v 3.94 4 4.06 t a = - 2 0 c to + 8 5 c v cc ? 3.6 v 3.92 4 4.08 t a = - 2 0 c to + 10 5 c v cc ? 3.6 v 3.9 4 4.1 t a = - 40 c to + 10 5 c 2.8 4 5.2 when not trimming frequency stabilization time t crwt - - - 30 s * 2 *1: in the case of using the values in cr trimming area of flash memory at shipment for frequency/t emperature trimming. *2: this is the time to stabilize the frequency of high - speed cr clock after setting trimming value. this period is able to use high - speed cr clock as source clock. x0 a
document number: 002 - 05655 rev. *d page 61 of 101 mb9b120m series built - in low - speed cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz 12.4.4 operating conditions of main pll (in the case of using main clock for input of pll) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - s pll input clock frequency f plli 4 - 16 mh z pll multiplication rate - 5 - 37 multiplier pll macro oscillation clock frequency f pllo 75 - 150 mh z main pll clock frequency* 2 f clkpll - - 72 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see " chapter: clock" in "fm3 family peripheral manual ". 12.4.5 operating conditions of main pll (in the case of using built - in high - speed cr for input clock of m ain pll ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiplication rate - 19 - 35 multiplier pll macro oscillation clock frequency f pllo 72 - 150 mh z main pll clock frequency* 2 f clkpll - - 72 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see "chapter 2 - 1 : clock" in "fm3 family peripheral manual ". note: make sure to input to the m ain pll source clock, the high - speed cr clock (clkhc) that the frequency /temperature has been trimmed. when setting pll multiple rate, please take the accuracy of the built - in high - speed cr clock into account and prevent the master clock from exceeding the maximum frequency. k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection
document number: 002 - 05655 rev. *d page 62 of 101 mb9b120m series 12.4.6 reset input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns 12.4.7 power - on reset timing (v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 1 - - ms *1 power ramp rate dv/dt v cc : 0.2 v to 2.70 v 0.3 - 1000 mv/s *2 time until releasing power - on reset t prt - 1.34 - 18.6 ms *1: v cc must be held below 0.2 v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of cold start (t off >1 ms). note: if t off cannot be satisfied designs must assert external reset(initx) at power - up and at any brownout event per 12.4.6. glossary ? vdh : detection voltage (when svhr=00000) of low - voltage detection reset . see " 12. 8. low - voltage detection characteristics " . v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 2 . 7 v
document number: 002 - 05655 rev. *d page 63 of 101 mb9b120m series 12.4.8 base timer input timing timer input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck , tin) - 2 t cycp - ns trigger input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note: t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is connected to, see " block diagram " in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 05655 rev. *d page 64 of 101 mb9b120m series 12.4.9 csio/uart timing csio (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc notes: the above characteristics apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time . about the apb bus number which multi - function serial is connected to , see " block diagram " in this data she et. these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. w hen the external load capacitance c l = 30 pf .
document number: 002 - 05655 rev. *d page 65 of 101 mb9b120m series master mode slave mode t slsh t shsl v ih t f t r v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi sck sot sin
document number: 002 - 05655 rev. *d page 66 of 101 mb9b120m series csio (spi = 0, scinv = 1 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc notes: the above characteristics apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see "block diagram" in this data sheet. these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. w hen the external load capacitance c l = 30 pf.
document number: 002 - 05655 rev. *d page 67 of 101 mb9b120m series master mode slave mode t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin
document number: 002 - 05655 rev. *d page 68 of 101 mb9b120m series csio (spi = 1, scinv = 0 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc notes: the above characteristics apply to clk synchronous mode . t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " block diagram " in this data sheet . these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. w hen the external load capacitance c l = 30 pf.
document number: 002 - 05655 rev. *d page 69 of 101 mb9b120m series master mode slave mode *: changes when writing to tdr register t f t r t slsh t shsl t shove v i l v i l v ih v ih v ih v oh * v o l v oh v o l v ih v i l v ih v i l t ivsle t slixe sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivsli t slixi sck sot sin
document number: 002 - 05655 rev. *d page 70 of 101 mb9b120m series csio (spi = 1, scinv = 1 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions v cc < 4.5 v v cc notes: the above characteristics apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " block diagram " in this data sheet. these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_ 1 is not guaranteed. w hen the external load capacitance c l = 30 pf.
document number: 002 - 05655 rev. *d page 71 of 101 mb9b120m series master mode slave mode uart e xternal clock input (ext = 1 ) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions min max unit remarks serial clock l pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock h pulse width t shsl t cycp + 10 - ns sck falling time t f - 5 ns sck rising time t r - 5 ns t shsl v i l v i l v i l v ih v ih t r t f t slsh s ck t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin
document number: 002 - 05655 rev. *d page 72 of 101 mb9b120m series 12.4.10 external input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl adtg - 2 t cycp * 1 - n s a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * 1 - ns waveform generator int xx, nmix *2 2 t cycp + 100* 1 - ns external interrupt nmi *3 500 - ns wkupx *4 500 - ns deep standby wake up *1: t cycp indicates the apb bus clock cycle time. about the apb bus number which the a/d converter, multi - function timer , external interrupt are connected t o , see " block diagram in this data sheet. *2: when in r un mode, in s leep mode. * 3 : when in s top mode, in rtl mode, in t imer mode. * 4 : when in deep s tandby rtc mode, in deep s tandby s top mode.
document number: 002 - 05655 rev. *d page 73 of 101 mb9b120m series 12.4.11 quadrature position/revolution counter timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions value unit min max ain pin h width t ahl - 2 t cycp * - ns ain pin l width t all - bin pin h width t bhl - bin pin l width t bll - bin rising time from ain pin h level t aubu pc_mode2 or pc_ m ode3 ain falling time from bin pin h level t buad pc_mode2 or pc_mode3 bin falling time from ain pin l level t adbd pc_mode2 or pc_mode3 ain rising time from bin pin l level t bdau pc_mode2 or pc_mode3 ain rising time from bin pin h level t buau pc_mode2 or pc_mode3 bin falling time from ain pin h level t aubd pc_mode2 or pc_mode3 ain falling time from bin pin l level t bdad pc_mode2 or pc_mode3 bin rising time from ain pin l level t adbu pc_mode2 or pc_mode3 zin pin h width t zhl qcr:cgsc=0 zin pin l width t zll qcr:cgsc=0 ain/bin rise and falling time from determined zin level t zabe qcr:cgsc=1 determined zin level from ain/bin rise and falling time t abez qcr:cgsc=1 *: t cycp indicates the apb bus clock cycle time. about the apb bus number which the quadrature position/revolution counter is connected t o , see " block diagram " in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 05655 rev. *d page 74 of 101 mb9b120m series zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 05655 rev. *d page 75 of 101 mb9b120m series 12.4.12 i 2 c timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (v p /i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda ; : scl ; t hdsta 4.0 - 0.6 - s scl clock l width t low 4.7 - 1.3 - s scl clock h width t high 4.0 - 0.6 - s (repeated) start condition setup time scl 9 : sda ; t susta 4.7 - 0.6 - s data hold time scl ; : sda ;9 t hddat 0 3.45* 2 0 0.9* 3 s data setup time sda ;9 : scl 9 t sudat 250 - 100 - ns stop condition setup time scl 9 : sda 9 t susto 4.0 - 0.6 - s bus free time between stop condition and start condition t buf 4.7 - 1.3 - s noise filter t sp - 2 t cycp * 4 - 2 t cycp * 4 - ns *1: r and c l represent the pull - up resistor and load capacitance of the scl and sda lines, respectively. v p indicates the power supply voltage of the pull - up resistor and i ol indicates v ol guaranteed current. *2: the maximum t hddat must satisfy that it does not extend at least l period (t low ) of device's scl signal. *3: a fast - speed mode i 2 c bus device can be used on a s tandard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat ?qv *4: t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is connected to, see " block diagram " in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more to use fast - mode , set the apb bus cloc k at 8 mhz or more. sda s cl
document number: 002 - 05655 rev. *d page 76 of 101 mb9b120m series 12.4.13 jtag timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max tms , tdi setup time t jtags tck , tms , tdi v cc ? 4.5 v 15 - ns v cc < 4.5 v tms , tdi hold time t jtagh tck , tms , tdi v cc ? 4.5 v 15 - ns v cc < 4.5 v tdo delay time t jtagd tck , tdo v cc ? 4.5 v - 25 ns v cc < 4.5 v - 45 note: when the external load capacitance c l = 30 pf. tck tms/ tdi tdo
document number: 002 - 05655 rev. *d page 77 of 101 mb9b120m series 12.5 12 - bit a/d converter electrical c haracteristics for the a/d c onverter (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 10 5 c) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 1.5 4.5 lsb avrh = 2.7 v to 5.5 v differential non linearity - - - 1.7 2.5 lsb zero transition voltage v z t an xx - 10 15 mv full - scale transition voltage v fst an xx - avrh 5 avrh 15 mv conversion time - - 0.8 * 1 - - s av cc ? 4.5 v 1.0 * 1 - - av cc < 4.5 v sampling time* 2 t s - 0.24 - 10 s av cc ? 4.5 v 0.3 - av cc < 4.5 v compare clock cycle* 3 t cck - 40 - 1000 ns av cc ? 4.5 v 50 - av cc < 4.5 v state transition time to operation permission t stt - - - 1.0 s analog input capacity c ain - - - 9.7 pf analog input resistor r ain - - - 1.7 k av cc ? 4.5 v 2.4 av cc < 4.5 v interchannel disparity - - - - 4 lsb analog port input leak current - a nxx - - 5 a analog input voltage - an xx av rl - avrh v reference voltage - avrh 2.7 - av cc v - avrl av ss - av ss v *1: the conversion time is the value of sampling time (t s ) + compare time (t c ). the condition of the minimum conversion time is the following. av cc ? v, hclk= 5 0 mhz sampling time: 240 ns , compare time: 560 n s . av cc < 4.5 v, hclk= 40 mhz sampling time: 3 00 ns, compare time: 700 ns ensure that it satisfies the value of the sampling time (t s ) and compare clock cycle (t cck ). for setting of the sampling time and compare clock cycle, see " chapter 1 - 1 : a/d converter " in " fm3 family peripheral manual analog macro part ". the register setting s of the a / d c onverter are reflected in the operation according to the apb bus clock timing. for the number of the apb bus to which the a/d converter is connected , see " block diagram ". the base clock (hclk) is used to generate the sampling time and the compare clock cycle. *2: a necessary sampling time changes by external impedance. ensure that it sets the sampling tim e to satisfy ( equation 1 ). *3: the compare time ( t c ) is the value of ( equation 2).
document number: 002 - 05655 rev. *d page 78 of 101 mb9b120m series (equation 1) t s ? ( r ain + r ext ) c ain 9 t s : sampling time r ain : i nput resistor of a/d = 1.5 k at 4.5 v < av cc < 5.5 v ch.0 to ch.7 i nput resistor of a/d = 1.6 k at 4.5 v < av cc < 5.5 v ch.8 to ch.15 i nput resistor of a/d = 1.7 k at 4.5 v < av cc < 5.5 v ch.16 to ch.26 i nput resistor of a/d = 2.2 k at 2.7 v < av cc < 4 .5 v ch.0 to ch.7 i nput resistor of a/d = 2.3 k at 2.7 v < av cc < 4 .5 v ch.8 to ch.15 i nput resistor of a/d = 2.4 k at 2.7 v < av cc < 4 .5 v ch.16 to ch.26 c ain : i nput capacity of a/d = 9.7 pf at 2.7 v < av cc < 5.5 v r ext : output impedance of external circuit (equation 2 ) t c = t cck 14 t c : compare time t cck : compare clock cycle c ain analog signal source an xx analog input pin c omparator r ext r ain
document number: 002 - 05655 rev. *d page 79 of 101 mb9b120m series definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition point (0b000000000000 8: 0b000000000001) and the full - scale transition point (0b111111111110 8: 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonl inearity of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential non linearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v zt 4094 n: a/d converter digital output value. v zt : voltage at whi ch the digital output ch anges from 0x000 to 0x001. v fst : voltage at whi ch the digital output ch anges from 0xffe to 0xfff. v nt : voltage at whi ch the digital output ch dqjhviurp[1 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff avrl avrh avrl avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 05655 rev. *d page 80 of 101 mb9b120m series 12.6 10 - bit d /a converter electrical ch aracteristics for the d /a converter ( v cc = av cc = 2.7 v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 10 5 c ) parameter symbol pin name value unit remarks min typ max resolution - dax - - 10 bit conversion time t c20 0. 4 7 0.5 8 0.69 s load 20 pf t c100 2.37 2. 90 3.4 3 s load 100 pf integral nonl inearity * 1 inl - 4.0 - + 4.0 lsb differential non linearity * 1, * 2 dnl - 0.9 - + 0.9 lsb output voltage offset v off - - 10.0 mv code is 0x000 - 20 .0 - + 5. 4 mv code is 0x3ff analog output impedance r o 3.10 3. 8 0 4.5 0 k d/a operation 2.0 - - m d/a stop output undefined period t r - - 70 ns *1: no - load *2: generates the max current by the code about 0x200
document number: 002 - 05655 rev. *d page 81 of 101 mb9b120m series 12.7 low - v oltage d etection ch aracteristics 12.7.1 l ow - v oltage d etection r eset ( t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr* 1 = 00000 2.25 2.45 2.65 v when voltage drops released voltage vdh 2.30 2.50 2.70 v when voltage rises detected voltage vdl svhr* 1 = 00001 2.39 2.60 2.81 v when voltage drops released voltage vdh 2.48 2.70 2.92 v when voltage rises detected voltage vdl svhr* 1 = 00010 2.48 2.70 2.92 v when voltage drops released voltage vdh 2.58 2.80 3.02 v when voltage rises detected voltage vdl svhr* 1 = 00011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhr* 1 = 00100 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhr* 1 = 00101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhr* 1 = 00110 3.31 3.60 3.89 v when voltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhr* 1 = 00111 3.40 3.70 4.00 v when voltage drops released voltage vdh 3.50 3.80 4.10 v when voltage rises detected voltage vdl svhr* 1 = 01000 3.68 4.00 4.32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhr* 1 = 01001 3.77 4.10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises detected voltage vdl svhr* 1 = 01010 3.86 4.20 4.54 v when voltage drops released voltage vdh 3.96 4.30 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 8160 t cycp * 2 s lvd detection delay time t lvddl - - - 200 s * 1 : the svhr bit of low - v oltage detection voltage control register (lvd_ctl) is initialized to "00000" by l ow - v oltage d etection r ese t . * 2 : t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 05655 rev. *d page 82 of 101 mb9b120m series 12.7.2 interrupt of l ow - v oltage d etection ( t a = - 40 c to + 105 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 00011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 00100 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 00101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhi = 00110 3.31 3.60 3.89 v when voltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhi = 00111 3.40 3 . 70 4.00 v when voltage drops released voltage vdh 3.50 3.80 4.10 v when voltage rises detected voltage vdl svhi = 01000 3.68 4 . 00 4.32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhi = 01001 3.77 4 . 10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises detected voltage vdl svhi = 01010 3.86 4 . 20 4.54 v when voltage drops released voltage vdh 3.96 4.30 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 8160 t cycp * s lvd detection delay time t lvddl - - - 200 s *: t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 05655 rev. *d page 83 of 101 mb9b120m series 12.8 flash memory write/erase ch aracteristics 12.8.1 write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter value unit remarks typ max sector erase time large sector 1.1 2.7 s includ es write time prior to internal erase small sector 0.3 0.9 half word (16 - bit) write time 16 310 s not including system - level overhead time chip erase time 6.8 18 s includes write time prior to internal erase *: the typical value is immediately after shipment , the maximum value is guarantee value under 10,000 cycle of erase/write . 12.8.2 write cycles and data hold time erase/write cycles (cycle ) data hold time (year ) remarks 1,000 20* 10,000 10* *: at average + 85 ?
document number: 002 - 05655 rev. *d page 84 of 101 mb9b120m series 12.9 return time from low - power consumption mode 12.9.1 return f actor: interrupt/wkup the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode t icnt t cycc s high - speed cr timer mode, main timer mode, pll timer mode 40 80 s low - speed cr timer mode 340 680 s sub timer mode 680 860 s rtc mode, stop mode 268 503 s deep standby rtc mode deep standby stop mode 308 583 s when ram is off 268 503 s when ram is on *: the maximum value depends on the accuracy of built - in cr. operation example of return from l ow - p ower consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05655 rev. *d page 85 of 101 mb9b120m series operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: the return factor is different in each low - power consumption modes. see "chapter 6: low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual . when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6: low power consumption mode" in "fm3 family peripheral manual ". i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05655 rev. *d page 86 of 101 mb9b120m series 12.9.2 return f actor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. return c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode t rcnt 148 263 s high - speed cr timer mode, main timer mode, pll timer mode 148 263 s low - speed cr timer mode 248 463 s sub timer mode 312 496 s rtc mode, stop mode 268 503 s deep standby rtc mode deep standby stop mode 308 583 s when ram is off 268 503 s when ram is on *: the maximum value depends on the accuracy of built - in cr. operation example of return from l ow - p ower consumption mode (by initx) ? i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e
document number: 002 - 05655 rev. *d page 87 of 101 mb9b120m series operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: the return factor is different in each low - power consumption modes. see "chapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual . when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "c hapter 6 : low power consumption mode" in "fm3 family peripheral manual ". the time during the power - on reset/low - voltage detection reset is excluded. see 12.4.7 power - on reset timing in 12.4 ac characteristics in 12 . electrical characteristics for the detail on the time during the power - on reset/low - voltage detection reset. when in recovery from reset, cpu changes to the high - speed cr r un mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the m ain pll clock stabilization wait time. the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e
document number: 002 - 05655 rev. *d page 88 of 101 mb9b120m series 13. ordering information part number on - chip flash memory on - chip sram package packing mb9bf 12 1 kqn - g - ave2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? ? ? ? ? ? ? ?
document number: 002 - 05655 rev. *d page 89 of 101 mb9b120m series 14. package dimensions package type package code lqfp 80 lqh080 002 - 11501 ** d i men s io n s m i n . n o m . m ax . 0 7 . 1 a a 1 0 . 0 5 0 . 1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 4 . 0 0 b s c . d 1 12.00 b s c . e 0 . 5 0 bs c e e 1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 0 . 3 0 0 . 5 0 0 . 7 0 1 4 . 0 0 b s c . 1 2 . 0 0 b s c . s y m b o l b o t t o m vie w a a 1 0 . 2 5 1 8 0 d 1 d e b d 0. 2 0 c a - b d 0. 1 0 c a - b d 0. 0 8 c a - b d e e 1 4 5 7 3 4 5 7 3 8 7 5 2 1 0 b s e c t i o n a - a ' c 9 2 s ea t i n g p l an e 0. 0 8 c a a ' 6 l 1 l s i de vie w t o p vie w 2 0 2 1 4 0 1 4 0 6 6 1 0 6 1 4 8 0 6 1 2 1 4 0 1 2 0 package ou t line, 80 le a d lq f p 12.0x12.0x1.7 mm lq h 080 r e v * *
document number: 002 - 05655 rev. *d page 90 of 101 mb9b120m series package type package code lqfp 80 lqj080 002 - 14043 ** d i mensions s y m b o l m i n . n o m . m ax . a 1 . 7 0 a 1 0 . 0 0 0 . 2 0 b 0 .1 6 0 .38 c 0 .0 9 0 .20 d 1 6.0 0 b s c d 1 1 4 . 0 0 bs c e 0.65 bsc e e 1 l 0 .4 5 0 .6 0 0 .75 l 1 0 . 3 0 0 . 5 0 0 . 7 0 1 6 . 0 0 bs c 1 4 . 0 0 bs c 0 . 3 2 0 8 d 1 d e 0 2 1 80 e e 1 4 5 7 4 5 7 3 0.2 0 c a - b d 3 b 0.1 0 c a - b d 8 7 5 2 2 a a ' s e a t i n g p l an e a a 1 0.2 5 1 0 b s e c t i o n a - a ' c 9 l1 l 6 0.1 0 c dd d c a - b d 1 21 40 41 60 61 2 0 2 1 4 0 0 6 1 4 8 0 6 1 14.0x14.0x1.7 mm l q j 080 r ev * * package ou t line, 8 0 lea d lq f p
document number: 002 - 05655 rev. *d page 91 of 101 mb9b120m series package type package code lqfp 64 lqd064 002 - 11499 ** d i m e nsion s s y m b o l min . n o m . max . 0 7 . 1 a a1 0.0 0 0.2 0 b 0.1 5 0. 2 c 0.0 9 0.2 0 d 12 . 00 bsc. d 1 10 . 00 bsc. e 0 .50 bsc e e1 l 0.4 5 0.6 0 0.7 5 l 1 0.3 0 0.5 0 0.7 0 12 . 00 bsc. 10 . 00 bsc. d 1 d e 1 1 6 6 4 4 5 7 e e 1 4 5 7 3 6 3 0.2 0 c a - b d b 0.1 0 c a - b d 0.0 8 c a - b d 8 7 5 2 a a 1 0 . 25 10 b se c t ion a-a ' c 9 l1 l 2 a a ' s e a t i n g plan e 0.0 8 c side v i e w top v i e w b o tt o m vie w 1 7 3 2 3 3 4 8 4 9 1 1 6 1 7 3 2 3 3 4 8 6 4 4 9 package ou t line, 64 le a d lq f p 10 . 0x10 . 0x1 . 7 mm l q d064 re v * *
document number: 002 - 05655 rev. *d page 92 of 101 mb9b120m series package type package code lqfp 64 lqg064 002 - 13881 ** dimensi o n sym b o l m i n . no m . m ax . a 1.7 0 a 1 0.0 0 0.2 0 b 0 . 2 7 0 . 3 2 0 . 3 7 c 0 . 0 9 0 . 20 d 14.00 bsc d 1 12.00 bsc e 0.65 bsc e e 1 l 0.4 5 0.6 0 0.7 5 l1 0.3 0 0.5 0 0.7 0 14.00 bsc 12.00 bsc 0 d 1 d e 1 16 64 e e 1 4 5 7 4 5 7 3 3 0.20 c a - b d b 0.10 c a - b d 0.13 c a - b d 8 7 5 2 2 0.10 c a a' s eati n g pla n e b s ec t i on a - a' c 9 a a 1 0.2 5 1 0 l1 l s i d e vie w t o p v i e w b o tt o m vie w 17 32 33 48 49 1 16 17 32 64 49 8 4 3 3 12 . 0x12 . 0x1 . 7 m m lq g 064 r ev * * package ou t line, 6 4 lea d lq f p
document number: 002 - 05655 rev. *d page 93 of 101 mb9b120m series package type package code qfn 64 vnc064 002 - 13234 ** dimen s io n s n o m. m i n . b e 6.00 bs c 9.00 bs c d a 1 a 9.00 bs c 0.00 sym b o l ma x . 0.90 0.05 0.50 bs c l 0.35 0.45 0.40 0.2 0 0.2 5 0.30 e d 2 2 6.00 bs c e n 64 0.20 ref r n d 1 6 b i late r al c o p l a n a r it y zo n e a p pli e s to the exposed heat p i n # 1 i d o n t o p w i l l b e l o c a t e d w i t h i n t h e i n d i c a t e d z o n e. m a x i m u m a l l o w a b l e b u r r i s 0 . 0 7 6 m m i n a l l d i r e c t i o n s. d i m e n s i o n " b " a p p l i e s t o m e t a l l i z e d t e r m i n a l a n d i s m eas ur ed n i s t h e t o t a l n u m b e r o f t e r m i n a l s . a l l d i m e n sio n s a r e i n m i l l i m e t e r s . d i m e n s i o n i n g a n d t o l e r a n c i n g c o n f o r m s t o a s m e y 1 4 . 5 m-1994 . n o tes: ma x . p a c k age w a r p age i s 0.05mm . 8 7 . 6 . 5 1 . 4 3 . 2 . 9 h a s t h e optio n a l r a d i u s o n t h e ot h e r e n d of t h e te rm i n a l , t h e d i me n sio n " b " s h o uld n ot b e me a s u r e d i n t h at r a d i u s a r ea. n d r e f e r s to t h e n u m b e r of t e rmi n als o n d s i d e or e side . s i n k slug a s w e ll a s t h e t e rminals . be tw een 0 . 15 and 0 . 30mm f r o m t erm i n a l ti p . if t h e t e rm i n a l s i de vie w b o tt om vie w t o p vie w d a e b 0. 1 0 c 2 x 0. 1 0 c 2 x 0. 1 0 c a a 1 0. 0 5 c c seating plan e d2 e 2 0. 1 0 c a b 0. 1 0 c a b 1 6 4 e b 0. 1 0 c a b 0. 0 5 c ( n d - 1 ) e index m ar k 8 4 5 l 9 1 6 1 7 3 2 8 4 3 3 4 9 6 4 4 9 1 6 3 3 1 4 8 1 7 3 2 p a c k a ge o ut l i n e , 64 l ea d q f n 9 . 0 x 9 . 0 x0 . 9 m m v nc 0 64 6 . 0 x6 . 0 m m e pa d ( s aw n ) r e v*. *
document number: 002 - 05655 rev. *d page 94 of 101 mb9b120m series package type package code lqfp 48 lqa048 002 - 13731 ** d i m e n si o n s s y m b o l m i n . n o m . m ax . a 1 . 7 0 a1 0 . 0 0 0 . 2 0 b 0 . 1 5 0 . 2 7 c 0 . 0 9 0 . 2 0 d 9 .00 bsc d 1 7.00 bsc e 0.50 bsc e e1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 0 . 3 0 0 . 5 0 0 . 7 0 9.00 bsc 7.00 bsc 0 8 d1 d e 1 1 2 4 8 e e 1 4 5 7 4 5 7 3 0 . 2 0 c a - b d 3 b 0 . 1 0 c a - b d 0 . 8 0 c a - b d 8 7 5 2 2 a a' s eat i n g plane a a 1 0.2 5 1 0 b s e c t i o n a - a' c 9 l 1 l 6 0 . 8 0 c 1 4 8 1 3 2 4 3 6 2 5 3 7 1 2 1 3 2 4 2 5 3 6 3 7 7 . 0x7 . 0x1 . 7 mm l q a048 r ev * * package ou t line, 4 8 lea d lq f p
document number: 002 - 05655 rev. *d page 95 of 101 mb9b120m series package type package code qfn 48 vna048 002 - 15528 ** d i m e n s i o ns n o m. m i n . b e 5 . 50 bs c 7 . 00 bs c d a 1 a 7 . 00 bs c 0. 0 0 s y m b o l m ax . 0. 9 0 0. 0 5 2 . d i m e n s i o n i n g a n d t o l e r a n c i n c c o n f o r m s t o a s m e y14 . 5-1994 . 3 . n i s t h e t o t a l n u m b e r o f t e r m i na l s . 4 . dim e n s i o n " b " a p p l i e s t o m e t a l l iz e d t e r m i n a l a n d is measure d b e t w e e n 0 . 1 5 a n d 0 . 3 0 m m f r o m t e r m i n a l t i p . i f t h e t e r m i n al ha s t h e o p t i o n a l r a diu s o n t h e o t h e r e n d o f t h e t e r m inal. th e d i m e n s i o n " b " s h o u l d n o t b e m e a s u r e d i n t h a t r a d i us area . 5 . n d r e f e r t o t h e n u m b e r o f t e r m i n a l s o n d o r e side . 6 . m a x . p a c k a g e w a r p a g e i s 0 . 0 5 mm. 1 . a l l d i m e n s i o n s a r e i n m i l l i m e t ers . 0 . 50 bs c l 0. 2 0 0. 2 5 0. 3 0 e d 2 2 5 . 50 bs c e r 0 . 20 re f 7 . m a xim u m a l l o w a b l e b u r r s i s 0 . 0 7 6 m m in a l l dir e c t ions . 8 . p i n #1 i d o n t o p wi ll be l o c ate d wit h i n i nd i c ate d zo n e . 9 . bil a t e r a l c o p l a n a r i t y z o n e a p p l ie s t o t h e e x posed hea t s i n k s l u g a s w e l l a s t h e t e r m i n a l s . 0. 4 0 0. 3 5 0. 4 5 n o t e 1 0 . j e d e c s p e c ification n o . ref : n / a s i d e view b o t t o m vie w t o p view d a e b 0 . 1 0 c 2 x 0 . 1 0 c 2 x 0 . 1 0 c a a 1 0 . 0 5 c c s eat i n g p l a n e d 2 e 2 0 . 1 0 c a b 0 . 1 0 c a b 1 4 8 e b 0 . 1 0 c a b 0 . 0 5 c r (nd-1 ) e i nd e x ma r k 8 4 5 9 l 9 1 2 1 3 2 4 3 6 2 5 3 7 p a c k a g e o u t l i n e , 4 8 l ea d q f n 7.0 x 7.0 x 0.9 mm v n a 0 48 5.5x 5 . 5 mm epad ( sa w n ) rev**
document number: 002 - 05655 rev. *d page 96 of 101 mb9b120m series package type package code fbga 96 fdg096 002 - 13224 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 2 0 0 . 0 0 0 . 5 0 bs c 0 . 5 0 bs c 0 . 3 0 9 6 1 1 0 . 4 0 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 1 5 m i n . - 5 . 0 0 bs c 5 . 0 0 bs c 1 1 6 . 0 0 bs c 6 . 0 0 bs c n o m . - 1 . 3 0 0 . 3 5 m ax . s e 0 . 0 0 0 . 2 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0.2 0 c 2 x b 0.2 0 c 2 x i n d e x m a r k p i n a 1 corner 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 96 x b 0.0 5 c a b 5 6 6 s i de vie w 0.2 0 c 0.0 8 c c deta i l a b o t t o m vie w t o p vie w deta i l a 6.0x6.0x1.3 m m f d g 096 r ev * * package ou t line, 9 6 ball f bga
document number: 002 - 05655 rev. *d page 97 of 101 mb9b120m series 15. major changes spansion publication number: ds706 - 00050 page section change results revision 1.0 - - 3uholplqdu\:'dwd6khhw 3 features a/d converter (max 26channels ) revised the conversion time : 1.0 s : 0.8 s 5 unique id added the " unique id " . 6 product lineup function added the " unique id " . 15 to 17 list of pin functions list of pin numbers corrected the i/o circuit type. corrected the pin state type. 32 list of pin functions ? ? ? ?
document number: 002 - 05655 rev. *d page 98 of 101 mb9b120m series page section change results 20 list of pin functions list of pin numbers corrected the pin number of zin1_1. 23 list of pin functions corrected the pin number of adtg_2. 28 corrected pin numbers of sin0_1 and sot0_1. 30 corrected the pin number of dtti0x_2. 36 i/o circuit type type h : revised the value of " tbd " . 43 handling devices sub crystal oscillator added the descriptions . 46 block diagram corrected the figure. - a/d activation compare: 3ch : 2ch 48 memory map memory map (2) added the explanatory note. 53 pin status i n each cpu state list of pin status added the pin function of selected analog output about type l. 54 corrected the footnote. s ub cr timer : low - speed cr tim er 56 electrical characteristics 2. recommended operating conditions added the note and f ootnote. corrected the value of analog reference voltage 3 avrh . min.: avss : 2.7 57 3. dc characteristics (1) current rating added notes and footnotes. added the remarks of icc. added the frequency of main clock crystal oscillator in remarks. 61 4. ac characteristics (2) sub clock input char acteristics added the footnote . 62 (3) built - in cr oscillation characteristics ? built - in high - speed cr added " frequency stabilization time " added notes and footnotes. 64 (6) power - on reset timing ad ded " timing until releasing power - on reset " added the timing chart 66 (8) csio timing corrected the title. uart timing : csio timing corrected the foot note . uart : multi - function serial 68,70,72 corrected the footnote . uart : multi - function serial 77 (11) i 2 c timing revised the condition . revised the footnote. 79 5. 12 - bit a/d converter electrical characteristics for the a/d converter changed the name of parameter. ? non linearity error : integral nonlinearity ? differential linearity error : differential nonlinearity changed the symbol. o f zero transition voltage. v ot : v zt changed the pin name. an00 to an26 : anxx corrected the value of v 0t, v fst, ts, tstt , and reference voltage. revised footnotes. 80 change the figure. an00 to an26 : anxx 81 definition of 12 - bit a/d converter terms ? linearity error : integral nonlinearity ? differential linearity error : differential nonlinearity v 0t
document number: 002 - 05655 rev. *d page 99 of 101 mb9b120m series page section change results 85 8. flash memory write/erase characteristics changed the title of chapter. main flash memory write/erase characteristics : flash memory write/erase characteristics 86 9. return time low - power consumption mode added the chapter 3 return time from low - power consumption mode . revision 3.0 2 features usb interface added the description of pll for usb 35, 36 i/o circuit type added about +b input 48 memory map memory map(2) added the summary of flash memory sector and the note 52 pin status in each cpu stae list of pin status changed the pin status of i - type 55, 56 electrical characteristics 1. absolute maximum ratings added the clamp maximum current added about +b input 58 - 60 electrical characteristics 3. dc characteristics (1) current rating changed the table format added main timer mode current moved a/d converter current moved d/a converter current 65 electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main pll (4 - 2) operating conditions of main pll added the figure of main pll connection 68 - 75 electrical characteristics 4. ac characteristics (7) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 76 electrical characteristics 4. ac characteristics (9) external input timing added input pulse width of wkupx pin 81 electrical characteristics 5. 12bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage added conversion time at avcc < 4.5v 92, 93 ordering information change to full part number note: please see document history about later revised information
document number: 002 - 05655 rev. *d page 100 of 101 mb9b120m series document history document title: mb9b120m series 32 - bit arm? cortex? - m3 fm3 microcontroller document number: 002 - 05655 revision ecn orig. of change submission date description of change ** - toyo 03/18/2015 migrated to cypress and assigned document number 002 - 05655. no change to document contents or format. *a 5171443 toyo 0 3 / 18 /201 6 updated to cypress format. *b 56534 70 hter 0 3 / 0 9 /201 7 ? modified rtc description in features, real - time clock(rtc). changed starting count value from 01 to 00. deleted second , or day of the week in the interrupt function. ( page 3 ) ? updated package code and dimensions as follows ( page 8 - 14 , 88 - 96 ) - fpt - 48p - m49 - > lqa048 - lcc - 48p - m73 - > vna048 - fpt - 64p - m38 - > lqd064 - fpt - 64p - m39 - > lqg064 - lcc - 64p - m24 - > vnc064 - fpt - 80p - m37 - > lqh080 - fpt - 80p - m40 - > lqj080 - bga - 96p - m07 - > fdg096 ? added notes for jtag. ( page 30 ) ? updated 12.4. 7 power - on reset timing. changed parameter from power supply rise time(tr) [ms] to power ramp rate(dv/dt) [mv/ s] and add some comments. ( page 62 ) ? added the baud rate spec in 12.4.9 csio/uart timing.( page 64 - 70 ) ? corrected the erroneous descriptions as follows. - j - tag - > jtag ( page 23 ) - analog port input current - > analog port input leak current ( page 77 ) *c 5787307 ysat 06/29/2017 adapted new cypress logo *d hual 02/09/2018 updated the sales information and legal 6064687
document number: 002 - 05655 rev. *d february 9 , 2018 page 101 of 101 mb9b120m series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products a rm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory m icrocontrollers cypress.com/m cu psoc cypress.com/psoc power management ics cypress.com/p mic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 mcu cypress developer community c ommunity | projects | video s | blogs | training | co mp onents technical support cypress.com/support a rm and cortex are registered trademarks of a rm limited (or its subsidiaries) in the u s and /or elsewhere . ? cypress semiconductor corporation, 2012 - 2018. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypre ss). this document, including any software or firmware included or referenced in this doc ument (software), is owned by cypress under the intellectual property laws and treaties of the united states and other coun tries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this para graph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the so ftware, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for s oftware provided in source code form, to modify and reproduce the software s olely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cyp ress hardware product units, and (2) under those claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for u se with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this doc ument or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. no computing device can be absolutely secure. therefore, despite security measures implemented in cypress hardware or software produc ts, cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a cypress product. in addition, the products described in these materials m ay contain design defects or errors known as errata which may cause the product to deviate from published specifications. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the applicatio n or use of any product or circuit described in this document. any information provided in this document, including any samp le design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this d ocument to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as cr itical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollu tion control or hazardous substances manage ment, or other uses where the failure of the device or system could cause personal injury, death, or property damage (uninte nded uses). a critical component is any component of a device or system whose failure to perform can be reasonably expected to ca use the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or r elated to all unintended uses of cypress products. you shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal i njury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the unit ed states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brands ma y be claimed as property of their respective owners.

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